Hello,
We are finalizing a carrier design hosting two XTRX modules (mini-PCIe)
behind a PCIe switch (Orange Pi 5 Ultra host) and intend to operate them
in deterministic phase-coherent mode.
Synchronization architecture:
- u-blox ZED-F20P (RTK GNSS) as master timing source
- 10 MHz reference distributed to both XTRX modules via mini-PCIe pin
19 (MHZ_IN) - 1PPS distributed via mini-PCIe pin 3 (1PPSI_GPIO1)
- Star topology with low-skew clock/PPS fanout buffers
- Matched-length PCB routing to each socket
- 1PPS derived deterministically from the same 10 MHz reference
- No U.FL sync paths; injection exclusively via mini-PCIe pins
Our expectation is that with shared 10 MHz and shared 1PPS, both boards
will: 1) Lock to the common frequency reference, 2) Align epoch
deterministically, 3) Exhibit stable, calibratable phase offsets
suitable for coherent MIMO.
Before freezing hardware, we would like confirmation that:
- 10 MHz on MHZ_IN is fully supported and recommended for multi-board
coherent operation, - 1PPS via 1PPSI_GPIO1 is the correct mechanism for deterministic time
alignment, - There are no known firmware, driver, or FPGA constraints that would
prevent stable multi-board phase coherence under this architecture.
We’s really appreciate any guidance to coherent multi-XTRX operation.
Thanks,
Tom