Dual XTRX Deterministic Coherent Operation

General Discussion
1

Hello,

We are finalizing a carrier design hosting two XTRX modules (mini-PCIe)
behind a PCIe switch (Orange Pi 5 Ultra host) and intend to operate them
in deterministic phase-coherent mode.

Synchronization architecture:

  • u-blox ZED-F20P (RTK GNSS) as master timing source
  • 10 MHz reference distributed to both XTRX modules via mini-PCIe pin
    19 (MHZ_IN)
  • 1PPS distributed via mini-PCIe pin 3 (1PPSI_GPIO1)
  • Star topology with low-skew clock/PPS fanout buffers
  • Matched-length PCB routing to each socket
  • 1PPS derived deterministically from the same 10 MHz reference
  • No U.FL sync paths; injection exclusively via mini-PCIe pins

Our expectation is that with shared 10 MHz and shared 1PPS, both boards
will: 1) Lock to the common frequency reference, 2) Align epoch
deterministically, 3) Exhibit stable, calibratable phase offsets
suitable for coherent MIMO.

Before freezing hardware, we would like confirmation that:

  • 10 MHz on MHZ_IN is fully supported and recommended for multi-board
    coherent operation,
  • 1PPS via 1PPSI_GPIO1 is the correct mechanism for deterministic time
    alignment,
  • There are no known firmware, driver, or FPGA constraints that would
    prevent stable multi-board phase coherence under this architecture.

We’s really appreciate any guidance to coherent multi-XTRX operation.

Thanks,

Tom

2

Since this is a mixture of hardware, gateware and software questions, tagging @zack , @VytautasB and @ricardas .

3

Apologies for bumping this.

I do need to make some decisions. We can create a disciplined (derived from 1PPS GNSS source) reference clock of a variety of frequencies (from miniature OCXO) suitable for distribution to both XTRX modules. But the biggest question, the elephant in the room as it were, remains, which is point 3 above, namely:

  1. Exhibit stable, calibratable phase offsets suitable for coherent MIMO.

Surely there must be a reference example somewhere since the board is marketed as being suitable for scalable solutions?

Thanks.

4

Hi @tfrond ,

To clarify the gateware perspective, are you targeting LimeSDR XTRX v1.3?

Regarding your architecture:

  • 10 MHz referece and mini-PCIe pin19 (PCIE_CLK_IN) - Yes, the gateware allows switching the LMS7002M PLL reference between the internal TCXO and an external source via this pin. While 10 MHz is within LMS7002 supported PLL reference frequency range I would recommend checking and verifying LMS7002 PLL lock range if it suites your needs with 10MHz reference.

  • 1PPS via 1PPSI_GPIO1 - yes, gateware supports selecting this GPIO to trigger a synchronous reset/alignment of the sample counters across multiple modules. While this architecture ensures the sample counters are aligned but to achieve true Phase Coherence for MIMO, you will likely still need a software-based calibration step.

5

I’ve tried to run two LimeSDR XTRXs coherently using GPSDO with two phase aligned outputs: one for clock with 26MHz and one for 1PPS. So I feed these to two XTRXs (through U.FL connectors) and they are pretty much phase aligned on the RX side (I’ve only tested RX), BUT they have initial random phase offset of several samples (my sampling frequency is 12MHz). This seem to change every time the RX stream is started. I’m assuming this has to do with clock domain crossings, but I would have thought that the phase error would be ±1 sample, yet it seems more than that in my case.

Tested on 3.5 GW.