Hey Ed,
unless you share some code it will be quite difficult to help you. Also you could mabye add a bit on your plans to use the LimeSDR as a periphal. Is it just GPIO access? Then probably you don’t even need to change gateware or LimeSuite, as GPIO accesses can handeled through the APIs.
Maybe you could have a quick look at my current project. I am implementaing a small DDS core inside the LimeSDR written in VHDL. The configuration is also done using registers accesed by the NIOS. One can achieve this without adding an extra port, simply by using the internal SPI bus. Starting from adress 224 (decimal) you can add your configuration registers. Use this module: https://github.com/myriadrf/LimeSDR-USB_GW/blob/master/src/spi/fpgacfg.vhd and adapt it to your needs. Then you can simply access these registers using SoapySDR or the LimeSuite API (without any changes):
SoapySDR::Device *m_sdr_dev;
m_sdr_dev->writeRegister("BBIC", p_addr, p_val);
m_sdr_dev->readRegister("BBIC", p_addr);
Link to my project (have a look at the block schematic and probably at src/ddscfg.vhd):
Hopefully I could help a bit 