Question about Limesuiteng-integration fork

Prajwal · 10 March 2026 14:48

Hi Ricardas,

Following up in this chat — I have made some progress but have run into a new (and deeper) problem that have traced down to the LimeSuiteNG driver . Sharing the full analysis.

New problem: TxLPF and RxLPF are bypassed every time.

Description :-

Case 1 :- When keeping the LimeSDR as UE and USRP as gNB → UE(Lime) was able to detect the gNB(USRP) , but UE’s uplink signal was not being able to detect by the gNB .

Case 2 :- When gNB as Lime and UE as USRP → UE(USRP) was not able to detect the gNB(Lime)

This narrowed the problem to → TX path Analysis .

Considering Case 2:- When checked , all the parameters that is mentioned in the configuration files was being set and was verified in LimeSuite GUI and at that frequency there was RF signature , that confirms the transmission.

Then was analysing the logs to understand what all has been set ,

Here found it strange that the TXLPF and RXLPF at start it is being set and later it is being bypassed.

When connected the board to LimeSuite GUI after running the stack , observed that DC corrector , Gain Corrector , Phase Corrector , CMIX and GFIRs are also bypassed.

I think this is the most probable cause that the TX path is getting corrupted.

I checked this with Band n78 as well as for band n40 and n41.Band n40 and 41 is well within the hardware capability of LimeSDR mini v2.4 . In all of the cases observed the same behaviour that the UE (USRP) was not able to detect the gNB(lime) , but the reverse i.e gNB(USRP) and UE (Lime) the gNB is being detected by the UE , but the gNB is not able to detect the acknowledgement .

And in all the above bands the logs show that the TXLPF and RXLPF was bypassed and the DC corrector , IQ corrector , Phase Corrector , CMIX and GFIRs are also bypassed.

Suspecting LimeSuiteNG functionality.

The gNB terminal logs(After device being detected):-

[HW] Available devices:
[HW] “Limesdr-mini_v2.4, media=USB3.0, addr=0403:601f, serial=00000000000013”
[HW] Connected: Limesdr-mini_v2.4, media=USB3.0, addr=0403:601f, serial=00000000000013
[HW] FPGA: StopStreaming
[HW] lms7002m_set_tx_lpf: bandwidth(20000000): LAD=140, H=0
[HW] INT 57, FRAC 385875, DIV_OUTCH_CGEN 18
[HW] CGEN_VCO 14720000 Hz, RefClk 40000000 Hz
[HW] Calibrating CG_IAMP_TBB:
[HW] CG_IAMP_TBB(1) RSSI:0x000053DB approx. -9.91 dBFS
[HW] CG_IAMP_TBB(2) RSSI:0x000057C0 approx. -9.51 dBFS
[HW] CG_IAMP_TBB(3) RSSI:0x00005D3B approx. -8.99 dBFS
[HW] CG_IAMP_TBB(4) RSSI:0x00006004 approx. -8.73 dBFS
[HW] CG_IAMP_TBB(5) RSSI:0x0000691E approx. -7.95 dBFS
[HW] CG_IAMP_TBB(6) RSSI:0x0000712F approx. -7.30 dBFS
[HW] CG_IAMP_TBB(7) RSSI:0x00007EC6 approx. -6.32 dBFS
[HW] CG_IAMP_TBB(8) RSSI:0x000087E4 approx. -5.72 dBFS
[HW] CG_IAMP_TBB(9) RSSI:0x000096C2 approx. -4.81 dBFS
[HW] CG_IAMP_TBB(10) RSSI:0x0000A280 approx. -4.16 dBFS
[HW] CG_IAMP_TBB(11) RSSI:0x0000B2D3 approx. -3.33 dBFS
[HW] lms7002m_set_rx_lpf: bandwidth(20000000): TIA_C=242, TIA_RCOMP=11, TIA_CCOMP=2, RX_L_C=59, RX_H_C=255
[HW] Sampling rate set(20.000 MHz): CGEN:160.000 MHz, Decim: 2^1, Interp: 2^1
[HW] INT 63, FRAC 0, DIV_OUTCH_CGEN 7
[HW] CGEN_VCO 0 Hz, RefClk 40000000 Hz
[HW] FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:4
[HW] CLK[3] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
[HW] CLK[3] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
[HW] CLK[3] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
[HW] CLK[3] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
[HW] FPGA PLL[0] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
[HW] FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:4
[HW] CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
[HW] CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
[HW] CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
[HW] CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
[HW] FPGA PLL[0] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
[HW] Rx channel0: dev0 chip0 ch0 , LO: 2351.670 MHz SR: 15.360 MHz BW: 10.000 MHz | path: 1(‘LNAH’)
[HW] Tx channel0: dev0 chip0 ch0 , LO: 2351.670 MHz SR: 15.360 MHz BW: 10.000 MHz | path: 1(‘Band1’)
[HW] dev0 configure.
[HW] FPGA: StopStreaming
[HW] lms7002m_set_tx_lpf: bandwidth(20000000): LAD=140, H=0
[HW] INT 57, FRAC 385875, DIV_OUTCH_CGEN 18
[HW] CGEN_VCO 14720000 Hz, RefClk 40000000 Hz
[HW] Calibrating CG_IAMP_TBB:
[HW] CG_IAMP_TBB(1) RSSI:0x00009273 approx. -5.07 dBFS
[HW] CG_IAMP_TBB(2) RSSI:0x00009419 approx. -4.97 dBFS
[HW] CG_IAMP_TBB(3) RSSI:0x000098A3 approx. -4.71 dBFS
[HW] CG_IAMP_TBB(4) RSSI:0x00009ACC approx. -4.58 dBFS
[HW] CG_IAMP_TBB(5) RSSI:0x0000A026 approx. -4.29 dBFS
[HW] CG_IAMP_TBB(6) RSSI:0x0000A445 approx. -4.07 dBFS
[HW] CG_IAMP_TBB(7) RSSI:0x0000ABAE approx. -3.69 dBFS
[HW] CG_IAMP_TBB(8) RSSI:0x0000AD9C approx. -3.59 dBFS
[HW] CG_IAMP_TBB(9) RSSI:0x0000B817 approx. -3.08 dBFS
[HW] lms7002m_set_rx_lpf: bandwidth(20000000): TIA_C=242, TIA_RCOMP=11, TIA_CCOMP=2, RX_L_C=59, RX_H_C=255
[HW] Sampling rate set(20.000 MHz): CGEN:160.000 MHz, Decim: 2^1, Interp: 2^1
[HW] INT 63, FRAC 0, DIV_OUTCH_CGEN 7
[HW] CGEN_VCO 0 Hz, RefClk 40000000 Hz
[HW] FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:4
[HW] CLK[3] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
[HW] CLK[3] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
[HW] CLK[3] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
[HW] CLK[3] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
[HW] FPGA PLL[0] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
[HW] FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:4
[HW] CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
[HW] CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
[HW] CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
[HW] CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
[HW] FPGA PLL[0] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
[HW] Set Rx LO frequency (2351670000 Hz)
[HW] VCOH skipped
[HW] SX VCO:4703340000 Hz, RefClk:40000000 Hz, INT:113, FRAC:611844, DIV_LOCH:0, EN_DIV2_DIVPROG:0
[HW] Tuning Rx VCOL (ICT_VCO:220):
[HW] TuneVCO(SXR) - searching interval [0:128]
[HW] binary search:
[HW] csw=64 cmphl=0
[HW] csw=96 cmphl=0
[HW] csw=112 cmphl=0
[HW] csw=120 cmphl=0
[HW] csw=124 cmphl=0
[HW] csw=126 cmphl=0
[HW] csw=127 cmphl=0
[HW] adjust with linear search:
[HW] CSW interval failed to lock
[HW] TuneVCO(SXR) - searching interval [128:256]
[HW] binary search:
[HW] csw=192 cmphl=3
[HW] csw=160 cmphl=0
[HW] csw=176 cmphl=0
[HW] csw=184 cmphl=2
[HW] csw=188 cmphl=3
[HW] csw=186 cmphl=2
[HW] csw=187 cmphl=2
[HW] adjust with linear search:
[HW] csw=183 cmphl=2
[HW] csw=182 cmphl=2
[HW] csw=181 cmphl=0
[HW] CSW: lowest=182, highest=187, will use=184
[HW] choosing wider CSW locking range: low=182, high=187
[HW] TuneVCO(SXR) - confirmed lock with final csw=184, cmphl=2
[HW] VCOL : csw=184 tune ok
[HW] Selected: VCOL, CSW_VCO: 184
[HW] Set Tx LO frequency (2351670000 Hz)
[HW] VCOH skipped
[HW] SX VCO:4703340000 Hz, RefClk:40000000 Hz, INT:113, FRAC:611844, DIV_LOCH:0, EN_DIV2_DIVPROG:0
[HW] Tuning Tx VCOL (ICT_VCO:220):
[HW] TuneVCO(SXT) - searching interval [0:128]
[HW] binary search:
[HW] csw=64 cmphl=0
[HW] csw=96 cmphl=0
[HW] csw=112 cmphl=0
[HW] csw=120 cmphl=0
[HW] csw=124 cmphl=0
[HW] csw=126 cmphl=0
[HW] csw=127 cmphl=0
[HW] adjust with linear search:
[HW] CSW interval failed to lock
[HW] TuneVCO(SXT) - searching interval [128:256]
[HW] binary search:
[HW] csw=192 cmphl=2
[HW] csw=224 cmphl=3
[HW] csw=208 cmphl=3
[HW] csw=200 cmphl=3
[HW] csw=196 cmphl=3
[HW] csw=194 cmphl=3
[HW] csw=193 cmphl=3
[HW] adjust with linear search:
[HW] csw=191 cmphl=3
[HW] CSW: lowest=192, highest=192, will use=192
[HW] choosing wider CSW locking range: low=192, high=192
[HW] TuneVCO(SXT) - narrow locking values range detected [192:192]. VCO lock status might change with temperature.
[HW] TuneVCO(SXT) - failed lock with final csw=192, cmphl=3
[HW] VCOL : failed to lock
[HW] VCOM skipped
[HW] VCOH skipped
[HW] SX VCO:4703340000 Hz, RefClk:40000000 Hz, INT:113, FRAC:611844, DIV_LOCH:0, EN_DIV2_DIVPROG:0
[HW] Tuning Tx VCOL (ICT_VCO:252):
[HW] TuneVCO(SXT) - searching interval [0:128]
[HW] binary search:
[HW] csw=64 cmphl=0
[HW] csw=96 cmphl=0
[HW] csw=112 cmphl=0
[HW] csw=120 cmphl=0
[HW] csw=124 cmphl=0
[HW] csw=126 cmphl=0
[HW] csw=127 cmphl=0
[HW] adjust with linear search:
[HW] CSW interval failed to lock
[HW] TuneVCO(SXT) - searching interval [128:256]
[HW] binary search:
[HW] csw=192 cmphl=3
[HW] csw=160 cmphl=0
[HW] csw=176 cmphl=0
[HW] csw=184 cmphl=2
[HW] csw=188 cmphl=2
[HW] csw=190 cmphl=3
[HW] csw=189 cmphl=2
[HW] adjust with linear search:
[HW] csw=183 cmphl=0
[HW] CSW: lowest=184, highest=189, will use=186
[HW] choosing wider CSW locking range: low=184, high=189
[HW] TuneVCO(SXT) - confirmed lock with final csw=186, cmphl=2
[HW] VCOL : csw=186 tune ok
[HW] Selected: VCOL, CSW_VCO: 186
[HW] lms7002m_set_rx_lpf: bandwidth(10000000): TIA_C=494, TIA_RCOMP=6, TIA_CCOMP=4, RX_L_C=221, RX_H_C=255
[HW] lms7002m_set_tx_lpf: bandwidth(10000000): LAD=46, H=0
[HW] INT 57, FRAC 385875, DIV_OUTCH_CGEN 18
[HW] CGEN_VCO 14720000 Hz, RefClk 40000000 Hz
[HW] Calibrating CG_IAMP_TBB:
[HW] CG_IAMP_TBB(1) RSSI:0x00011B26 approx. +0.66 dBFS
[HW] lms7002m_set_rx_lpf: RxLPF bypassed
[HW] lms7002m_set_tx_lpf: TxLPF bypassed.
[HW] INT 57, FRAC 385875, DIV_OUTCH_CGEN 18
[HW] CGEN_VCO 14720000 Hz, RefClk 40000000 Hz
[HW] Calibrating CG_IAMP_TBB:
[HW] CG_IAMP_TBB(1) RSSI:0x000014A2 approx. -22.09 dBFS
[HW] CG_IAMP_TBB(2) RSSI:0x000022E0 approx. -17.53 dBFS
[HW] CG_IAMP_TBB(3) RSSI:0x00003763 approx. -13.51 dBFS
[HW] CG_IAMP_TBB(4) RSSI:0x000046D1 approx. -11.38 dBFS
[HW] CG_IAMP_TBB(5) RSSI:0x00005AED approx. -9.21 dBFS
[HW] CG_IAMP_TBB(6) RSSI:0x00006902 approx. -7.96 dBFS
[HW] CG_IAMP_TBB(7) RSSI:0x00007D63 approx. -6.41 dBFS
[HW] CG_IAMP_TBB(8) RSSI:0x00008B0A approx. -5.52 dBFS
[HW] CG_IAMP_TBB(9) RSSI:0x00009F06 approx. -4.35 dBFS
[HW] CG_IAMP_TBB(10) RSSI:0x0000ACE5 approx. -3.62 dBFS
[HW] CG_IAMP_TBB(11) RSSI:0x0000C11A approx. -2.66 dBFS
[HW] Sampling rate set(15.360 MHz): CGEN:491.520 MHz, Decim: 2^3, Interp: 2^3
[HW] INT 48, FRAC 159383, DIV_OUTCH_CGEN 1
[HW] CGEN_VCO 6080000 Hz, RefClk 40000000 Hz
[HW] FPGA SetPllFrequency: PLL[0] input:15.360 MHz clockCount:4
[HW] CLK[3] Fout:15.360 MHz bypass:0 phase:108.506 findPhase: 1
[HW] CLK[3] Fout:15.360 MHz bypass:0 phase:108.506 findPhase: 1
[HW] CLK[3] Fout:15.360 MHz bypass:0 phase:108.506 findPhase: 1
[HW] CLK[3] Fout:15.360 MHz bypass:0 phase:108.506 findPhase: 1
[HW] FPGA PLL[0] M=83, N=1, Fvco=1274.880 MHz (Requested 1274.880 MHz)
[HW] FPGA SetPllFrequency: PLL[0] input:15.360 MHz clockCount:4
[HW] CLK[1] Fout:15.360 MHz bypass:0 phase:93.7726 findPhase: 1
[HW] CLK[1] Fout:15.360 MHz bypass:0 phase:93.7726 findPhase: 1
[HW] CLK[1] Fout:15.360 MHz bypass:0 phase:93.7726 findPhase: 1
[HW] CLK[1] Fout:15.360 MHz bypass:0 phase:93.7726 findPhase: 1
[HW] FPGA PLL[0] M=83, N=1, Fvco=1274.880 MHz (Requested 1274.880 MHz)
[HW] FPGA SetPllFrequency: PLL[0] input:15.360 MHz clockCount:4
[HW] CLK[3] Fout:15.360 MHz bypass:0 phase:108.506 findPhase: 1
[HW] CLK[3] Fout:15.360 MHz bypass:0 phase:108.506 findPhase: 1
[HW] CLK[3] Fout:15.360 MHz bypass:0 phase:108.506 findPhase: 1
[HW] CLK[3] Fout:15.360 MHz bypass:0 phase:108.506 findPhase: 1
[HW] FPGA PLL[0] M=83, N=1, Fvco=1274.880 MHz (Requested 1274.880 MHz)
[HW] FPGA SetPllFrequency: PLL[0] input:15.360 MHz clockCount:4
[HW] CLK[1] Fout:15.360 MHz bypass:0 phase:93.7726 findPhase: 1
[HW] CLK[1] Fout:15.360 MHz bypass:0 phase:93.7726 findPhase: 1
[HW] CLK[1] Fout:15.360 MHz bypass:0 phase:93.7726 findPhase: 1
[HW] CLK[1] Fout:15.360 MHz bypass:0 phase:93.7726 findPhase: 1
[HW] FPGA PLL[0] M=83, N=1, Fvco=1274.880 MHz (Requested 1274.880 MHz)
[HW] chip0 ch0 Rx gain set LNA:15, PGA:31
[HW] chip0 ch0 Tx gain set MAIN:13, LIN:13
[HW] FPGA: StopStreaming
[HW] FPGA: StopWaveformPlayback
[HW] FPGA: ResetPacketCounters
[HW] FPGA: ResetTimestamp
[HW] USB ep:83 Rx0 Setup: usePoll:1 rxSamplesInPkt:1360 rxPacketsInBatch:1, DMA_ReadSize:4096, link:I12, batchSizeInTime:88.5417us FS:15360000.000000, FIFO=2823*1360
[HW] RxSetup wait for Rx worker thread.
[HW] Rx worker thread ready.
[HW] Tx0 Setup: samplesInTxPkt:1360 maxTxPktInBatch:5, batchSizeInTime:442.708us
[HW] TxSetup wait for Tx worker.
[HW] Tx worker thread ready.
[HW] Port[0] Stream samples format: I12 , link: I12
[HW] [RAU] has loaded LMSSDR device.
[PHY] RU 0 Setting N_TA_offset to 200 samples (UL Freq 2347350, N_RB 24, mu 1)
[PHY] Signaling main thread that RU 0 is ready, sl_ahead 6
[PHY] L1 configured without analog beamforming
[PHY] Attaching RU 0 antenna 0 to gNB antenna 0
[UTIL] threadCreate() for Tpool0_-1: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for Tpool1_-1: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for Tpool2_-1: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for Tpool3_-1: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for Tpool4_-1: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for Tpool5_-1: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for Tpool6_-1: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for Tpool7_-1: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for L1_rx_thread: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for L1_tx_thread: creating thread with affinity ffffffff, priority 97
[UTIL] threadCreate() for L1_stats: creating thread with affinity ffffffff, priority 1
TYPE TO TERMINATE
[PHY] got sync (L1_stats_thread)
[PHY] got sync (ru_thread)
[HW] FPGA: StartStreaming
[PHY] RU 0 rf device ready
[PHY] RU 0 RF started cpu_meas_enabled 0
[HW] Rx receive loop start.
[HW] Tx transmit loop start.
[PHY] Command line parameters for OAI UE: -C 2351670000 -r 24 --numerology 1 --ssb 0
[HW] USB ep:83 Rx0: 46.260 MB/s | TS:15357120 pkt:11293 o:0(+0) l:0(+0) dma:11293/11294(+1) swFIFO:0
[HW] USB ep:03 Tx0: 34.250 MB/s | TS:15398400 pkt:8397 u:0(+0) l:0(+0) dma:1794/1799(+5) tsAdvance:+2015/+2276/+2541us, f:0
[NR_MAC] Frame.Slot 128.0

The Complete gNB logs:-

Prajwal · 15 April 2026 10:35

Hi Ricardas,

Thank you for your guidance and support. I was able to successfully set up the LimeSDR Mini v2.4 as a gNodeB, establish a connection with the UE, and establish a PDU session.

Thank you

Redferne · 17 April 2026 02:02

Hi. Sorry for hijacking the thread. I have similar problems with getting UE to find the 5G SA cell in N78. I’ve tried two modems RM520N-GL and SIM8262E. They both work fine on N78 on a separate network. I would be very happy if someone could have a look at the gNB log over here: [HW] Version: Branch: limesuiteng-integration Abrev. Hash: d948c2962f Date: - Pastebin.com

I’m running a LimeSDR USB v1.4. To me it looks OK. But none of the modems are able to see the 20MHz cell @ 636672.

Here is another attempt on N40 using a 10MHz carrier, attempting to mimic @Prajwal success by analyzing the logs posted previously. CMDLINE: "/home/redferne/code/openairinterface5g/cmake_targets/ran_build/build/n - Pastebin.com

andrewback · 17 April 2026 08:21

Are you using an external reference such as GPSDO or just using the LimeSDR USB as-is?

Redferne · 17 April 2026 17:39

As is. No GPS reference. I had it working srsRAN/LTE a few years back without issues. I know some kind of reference is needed for commercial 5G SA TDD but I was hoping I could get away with none Any tips would be very welcome.

andrewback · 17 April 2026 17:58

This may not be the cause, but frequency accuracy is a possibility. Also crystal oscillators age over time, so while it’s not certain, it’s possible that this could explain why it once worked and now doesn’t. If this is the cause there are two potential fixes:

Use a GPSDO
Ascertain the frequency error and program this value to EEPROM so that the on-board DAC adjusts the VCTCXO accordingly. You should only have to do this once, or well, periodically I guess.

Redferne · 17 April 2026 23:26

Happy days! I created a gNB config on FDD N28 10MHz and lo and behold. The RM520 modem attached nicely. The SIM8262E does not however. I might need to tinker with TX/RX Gain as there are other carriers on N28 around. Would you be so kind to help me understand these parameters:
Lime Radio config:
tx_gain= 20.0;
rx_gain= 50.0;
oai5g gNB config:
att_tx = 0;
att_rx = 0;
max_rxgain = 125;
How are they related and what are they exactly doing. Gain or attenuation? Are my parameters reasonable or what do I need to change?

Have a lovely weekend. I sure will

Oh, and where can I find a reasonable priced GPSDO in europe these days?

andrewback · 19 April 2026 15:49

@Karolis could you advise please.

The Leo Bodnar GPSDOs seem to be popular.

Karolis · 20 April 2026 07:38

Hello,

Lime Radio config:

tx_gain= 20.0; – SDR transmitter (from gNB side downlink) analog output power control. Control value from 0-50, where 50 max. Controls in 1dB steps, except 39-0, where every change in steps of 2 changes gain value by 2 dB (38, 36, 34, 32 and so on)
rx_gain= 50.0; – SDR receiver (from gNB side uplink) analog gain control. Control value from 0-50, where 50 max. Controls in 1dB steps.

Recommended initial values for close tests are:

TX 50 for 1.8GHz and above, 40 for 2GHz and bellow

RX 20 for 1.8GHz and above, 9 for 2GHz and bellow (RX is complicated in OAI use case since they have large SNR requirements, so higher RX values are sometimes needed for OAI to work)

oai5g gNB config:
att_tx = 0;
att_rx = 0;
max_rxgain = 125;

Nothing is important here, since this is used for general use case USRP implementation, which in LimeSDR case, is bypassed.

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