The transactSPI call can actually hit the spi bus for the LMS7002m. Read/write registers was actually tied to the FPGA register space in this case. But I thought that this wasnt very useful. So if you pull latest master, you can hit the LMS7002m register space through read/write register, just use the “RFIC0” interface name first. Example:
python -c "import SoapySDR; d = SoapySDR.Device(); print(hex(d.readRegister('RFIC0', 0x20)))"
The explicit way would be to hit these register via a writeSettings() call. Further, I wanted to make it automatic when both rx and tx LOs are turned to the same frequency. If you want the same frequency setting, then it should be OK to just share a single LO in this case. I hope that seems intuitive. I’m also doing this for skylark (iris - another lms7 based design).
Let me know how your investigation with the SPI settings goes.