LIMESDR USB RF Loopback Test FAILED

Projects LimeSDR
1

[ TESTING STARTED ]
->Start time: Sat Feb 2 19:43:13 2019

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, serial=0009070105C51811, index=0
Serial Number: 0009070105C51811

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 31169; 34925; 38681 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112902 (min); 5113032 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 02 07 12 02 07 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-15.7 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-18.1 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-19.1 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-24.3 dBFS, 5.00 MHz) - FAILED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-31.1 dBFS, -0.01 MHz) - FAILED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-48.8 dBFS, 13.63 MHz) - FAILED
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 2.03 seconds

2

+1

[ TESTING STARTED ]
->Start time: Sun Mar 10 10:50:39 2019

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, serial=0009070105C61F0B, index=0
Serial Number: 0009070105C61F0B

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 30472; 34228; 37984 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112948 (min); 5113076 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 02 09 12 02 09 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-15.5 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-17.3 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-30.7 dBFS, 5.00 MHz) - FAILED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-32.7 dBFS, 5.00 MHz) - FAILED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-18.0 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-15.5 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 6.47 seconds

3

Hi @cmrincon,

Arrange RMA with Crowd Supply, please.

4

Hi @ThatGreeneDude,

Arrange RMA with Crowd Supply, please.

5

Should the antenna cables change the test result?
I use 50 ohm 10 cm long cable and With cable i got ~ -26dbfs, without cable ~ -20 dbfs.
I discovered that Temperature modify the results also.

Is the result fine? Should i arrange a RMA?

6

On LimeSDR-USB antennas or cables connected to RF port affect test results so the test should be performed without anything connected.

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