Is the PLL really locked?

Projects LimeSDR
1

Dear All,
I am using 4 LIMESDR-USB’s in a system (2 are TX and 2 are RX only).
I am programming them using the LIME API functions. (dll version is 19.04)
I suspect the PLL’s are not locking (for SXR).
The VCO tunes fine for the selected frequency but the “failed to lock” indication never disappears.
Here is the debug output:

[17:10:35] DEBUG: Estimated reference clock 30.6589 MHz
[17:10:35] INFO: Reference clock 30.72 MHz
[17:10:35] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.21 Ref Clk: 30.72 MHz
[17:10:57] DEBUG: INT 68, FRAC 948906, DIV_OUTCH_CGEN 3
[17:10:57] DEBUG: VCO 2147.48 MHz, RefClk 30.72 MHz
[17:10:57] DEBUG: csw 108; interval [105, 111]
[17:10:57] INFO: CGEN frequency set to 268.434998 MHz
[17:10:59] DEBUG: csw 108; interval [105, 111]
[17:11:10] DEBUG: INT 146, FRAC 211899, DIV_LOCH 5, EN_DIV2_DIVPROG 0
[17:11:10] DEBUG: VCO 4614.21 MHz, RefClk 30.72 MHz
[17:11:10] DEBUG: ICT_VCO: 192
[17:11:10] DEBUG: csw=64 cmphl=0
[17:11:10] DEBUG: csw=96 cmphl=0
[17:11:10] DEBUG: csw=112 cmphl=0
[17:11:10] DEBUG: csw=120 cmphl=0
[17:11:10] DEBUG: csw=124 cmphl=0
[17:11:10] DEBUG: csw=126 cmphl=0
[17:11:10] DEBUG: csw=127 cmphl=0
[17:11:10] DEBUG: Failed to lock
[17:11:10] DEBUG: csw=192 cmphl=3
[17:11:10] DEBUG: csw=160 cmphl=0
[17:11:10] DEBUG: csw=176 cmphl=3
[17:11:10] DEBUG: csw=168 cmphl=2
[17:11:10] DEBUG: csw=172 cmphl=2
[17:11:10] DEBUG: csw=174 cmphl=3
[17:11:10] DEBUG: csw=173 cmphl=3
[17:11:10] DEBUG: Failed to lock
[17:11:10] DEBUG: cmphl=2
[17:11:10] DEBUG: VCOL : csw=170 tune ok
[17:11:10] DEBUG: ICT_VCO: 192
[17:11:10] DEBUG: TuneVCO(SXR) - VCO too high
[17:11:10] DEBUG: VCOM : csw=0 tune fail
[17:11:10] DEBUG: ICT_VCO: 192
[17:11:10] DEBUG: TuneVCO(SXR) - VCO too high
[17:11:10] DEBUG: VCOH : csw=0 tune fail
[17:11:10] DEBUG: Selected: VCOL
[17:11:10] INFO: SXR frequency set to 72.097000 MHz
[17:11:17] DEBUG: ICT_VCO: 192
[17:11:17] DEBUG: csw=64 cmphl=0
[17:11:17] DEBUG: csw=96 cmphl=0
[17:11:17] DEBUG: csw=112 cmphl=0
[17:11:17] DEBUG: csw=120 cmphl=0
[17:11:17] DEBUG: csw=124 cmphl=0
[17:11:17] DEBUG: csw=126 cmphl=0
[17:11:17] DEBUG: csw=127 cmphl=0
[17:11:17] DEBUG: Failed to lock
[17:11:17] DEBUG: csw=192 cmphl=3
[17:11:17] DEBUG: csw=160 cmphl=0
[17:11:17] DEBUG: csw=176 cmphl=3
[17:11:17] DEBUG: csw=168 cmphl=2
[17:11:17] DEBUG: csw=172 cmphl=2
[17:11:17] DEBUG: csw=174 cmphl=3
[17:11:17] DEBUG: csw=173 cmphl=3
[17:11:17] DEBUG: Failed to lock
[17:11:17] DEBUG: cmphl=2

2

Hi @Crater,

Could you post LimeQuickTest log here, please.

3

Dear all,
I have the same situation with LimeSDR USB.
→ Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.23 Ref Clk: 30.72 MHz
I’m programming with LMS API and if I try SetLOFrequency to 2399.4 MHz, I get a lot of messages failed to lock
What can I do to fix it?

Thanks in advance
Estimated reference clock 30.6587 MHz
Reference clock 30.72 MHz
SetFrequencySXR, INT 152, FRAC 228010, DIV_LOCH 0, EN_DIV2_DIVPROG 0
Expected VCO 4799.00 MHz, RefClk 30.72 MHz
Tuning VCOL :
TuneVCO(SXR) ICT_VCO: 128
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64 cmphl=0
csw=96 cmphl=0
csw=112 cmphl=0
csw=120 cmphl=0
csw=124 cmphl=0
csw=126 cmphl=0
csw=127 cmphl=0
adjust with linear search:
CSW interval failed to lock
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192 cmphl=0
csw=224 cmphl=3
csw=208 cmphl=3
csw=200 cmphl=2
csw=204 cmphl=3
csw=202 cmphl=2
csw=203 cmphl=2
adjust with linear search:
csw=199 cmphl=2
csw=198 cmphl=2
csw=197 cmphl=0
CSW: lowest=198, highest=203, will use=200
choosing wider CSW locking range: low=198, high=203
TuneVCO(SXR) - confirmed lock with final csw=200, cmphl=2
VCOL : csw=200 tune ok
Tuning VCOM :
TuneVCO(SXR) ICT_VCO: 128
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64 cmphl=3
csw=32 cmphl=0
csw=48 cmphl=2
csw=56 cmphl=2
csw=60 cmphl=2
csw=62 cmphl=2
csw=63 cmphl=2
adjust with linear search:
csw=47 cmphl=0
CSW: lowest=48, highest=63, will use=55
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=3
csw=144 cmphl=3
csw=136 cmphl=3
csw=132 cmphl=3
csw=130 cmphl=3
csw=129 cmphl=3
adjust with linear search:
CSW interval failed to lock
choosing wider CSW locking range: low=48, high=63
TuneVCO(SXR) - confirmed lock with final csw=55, cmphl=2
VCOM : csw=55 tune ok
Tuning VCOH :
TuneVCO(SXR) ICT_VCO: 128
TuneVCO(SXR) - attempted VCO too high
VCOH : failed to lock

4

This is expected, these are debug messages. There are three VCOs: VCOL, VCOM, VCOH. When setting LO frequency, one of those VCOs needs to be selected, they have frequency overlaps, so all of them are attempted to be tuned, and the one with best values is chosen from the successfull tunes.

5

Hi @ricardas, thank you very much for a quick response.