External 10 MHz Clock on LimeSDR Mini 2.0

Projects LimeSDR
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LimeSDR Mini 2.0: my 10 MHz external reference doesn’t lock the clockgen PLL

My 10 MHz external reference doesn’t lock the clockgen (CGEN) PLL on the LimeSDR Mini 2.0.

Setup: LimeSDR Mini 2.0 (hardware v7, gateware 2.6, firmware 10), LimeSuiteNG built from
source on Windows, 10 MHz into REFCLK IN J8.

What works:

  • External reference path enables via FPGA register 0x00CF[0] = 1.
  • The board measures the reference correctly: the FPGA counter reads ~10.0003 MHz.
  • Internal 40 MHz VCTCXO: everything configures and streams normally.

What fails: with the external 10 MHz selected, every configuration attempt dies at the
CGEN tune step:

> limeConfig --initialize --refclk=10e6 --samplerate=5e6 --rxen=1 --rxlo=1.4e9 --rxpath=LNAH
lms7002m_set_frequency_cgen:(160000000 Hz) failed
lms7002m_set_frequency_cgen:(61440000 Hz) failed
lms7002m_set_frequency_cgen:(40000000 Hz) failed
Failed to configure device (chip0)

Probing over SPI: sweeping the CGEN cap bank (CSW_VCO_CGEN, 0x008B[8:1]) while reading the
VCO comparator (0x008C[13:12]) shows a normal lock window on internal 40 MHz (comparator
transitions 00 → 10 → 11, window near CSW ≈ 170), but on external 10 MHz the comparator is railed at 00 across the entire cap bank — no lock window exists anywhere.

Already ruled out:

  • Loop filter / charge pump / VCO bias (swept CP2/CP3/CZ, IPULSE_CP_CGEN, ICT_VCO_CGEN,
    individually and combined — comparator still railed everywhere)
  • Integer-N mode (frac = 0) — no change
  • Different CGEN targets (sample rates 2–30.72 MS/s) — all fail
  • Bad board — three separate Mini 2.0 units fail identically; all three lock fine on
    their internal 40 MHz
  • Drive level (3 dB pad in-line — no change)

Questions:

  1. Is a raw 10 MHz reference supported on the Mini 2.0, or do I need 30.72 / 38.4 / 40 MHz external clock source instead?
  2. If 10 MHz should work, what’s the correct procedure?

Thanks!

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Tagging @Zack.