According to “LimeSDR-Mini v1.2 hardware description”, section 4.6 on clock distribution, to enable external reference clock: “VCTCXO can be disconnected from clock buffer input (remove R59 and solder R62) and external reference clock can be supplied from connector J8 (REF_CLK_IN).”
However, there doesn’t appear to be an unsoldered R62. Does anyone else see where an unsoldered R62 is located? The silkscreen label is in the middle, underneath the FPGA and without any nearby pads. Also, have I located the correct location of R59? I don’t see board design files for LimeSDR mini 1.2 (only LimeSDR mini 1.1).
Check the picture below, R59 and R62 are enclosed in red square. Actually, there are 3 pads for 2 resistors hence only one is possible to mount at a time. When it is fitted as it is now (horizontally), it means R59. If you fit it vertically as shown by green line in the picture it means R62 is fitted. This is what silkscreen is trying to explain
Hi @Zack - so because of the lack of the additionial clock control circuitry present on the LimeSDR-USB, I’m guessing the lime mini will only work with a 40MHz external reference clock?
I couldn’t find any clarification of this on the hardware description page.
Has anyone who has managed to run the LimeSDR-Mini from an external clock be willing to share their experience?
My understanding is that a reference clock of 10MHz is too low to run the LMS7002 successfully. Temperature fluctuations cause my VCTCXO output freq to drift such that my sample rate varies by 10S/s at 30.72MS/s over a range of around 5 degrees C about room temperature, which is not good enough for what I’m doing.
I could potentially trim the VCTCXO but would rather just use a freq ref instead.
I can confirm that it is working. We swapped the resistors and connected external 30.72MHz clock produced by LEA-M8F to REF CLK input. To verify we count the samples between two 1PPS signals. Now it is exactly 1/sample rate, before we saw an offset of a few samples.
I’m want to use the LimeSDR mini for operation with the Es’Hail2 (OSC100) Satellite. I understand I will have to use an external reference - I have purchased the Leo Bodnar GPS reference. The GPS unit can produce a 40MHz reference at a suitable level (it specify’s 8mA which equates to +7.7dBm) .
The problem
The U.FL connection was fiddly enough, but the change required to move R59 to R62 is impossible from my standpoint without damaging the board.
Can you recommend anyone who would do this for me? I understand that available space made this compromise, but 3 pins and a push on link would have been better.
Thank you for replying so quickly. One question I forgot to ask. What is the value of R59/R62, since it would seem appropriate to replace it rather than to move it?
It is 0Ohm.
You can check it in the schematic or BOM.
It is tiny part (0402) hence you can just put a solder blob instead of R62. Not very nice suggestion, but it will do the job.
This clock is used for NIOS CPU (FPGA internal). It will work, but NIOS CPU performance will be affected. You have to change reference clock for PLLs frequency calculation too.
I have carried out a variety of hardware modifications to the LimeSDR such as rotating R59 and also replacing the on-board DAC used to trim the VCTCXO. With the proper equipment rotating R59 is a relitivly easy task. I’d be happy to do this for you for a small fee, if you are interested then send me a PM.
Thanks Zack, that does not sound very viable to me.
As most of the precise clock sources available are mostly 10MHz units, it would have been nice to highlight on the spec sheet, that those are unusable, so the clock in can practically only be used to sync Minis to each other. Also highlighting that this needs a HW mod would be informative. If I would have known this, I would not bought the Mini… I guess the “big” LimeSDR can be driven from a 10MHz source without HW/SW mods.
I think the best what I can do is to sync my VSA to my 10MHz ref, measure the Mini with it, and trim the VCTXO as close to it as its possible. FYI, out of the box, my Mini has a 12kHz freq error on 2GHz…
The LimeSDR-Mini uses the 8-bit DAC5311 to trim the VCTCXO. The 12-bit DAC7311 is pin compatible so I swapped the ICs over.
You have to change the SPI driver that the NIOS uses to set the DAC output value but this is quite simple and just requires some minor modifications to the NIOS source code and then the FPGA image rebuilding and flashing.
I found that with an 8-bit DAC the LSB resolution was around 3-4 Hz, but with a 12-bit DAC it was around 0.25-0.5 Hz which made tuning the VCTCXO much easier. I was able to lock the VCTCXO to within 0.25 Hz of my PPS signal averaged over 30s using the 12-bit DAC, somthing that would have been impossible using the 8-bit version.
You’re litterally just changing the bytes that are sent over SPI to the DAC so the output value is in the required format for the 7311 as opposed to the 5311.
Apologies, it’s been a while since I looked at this - the code linked above is actually allowing the C++ API to read the current DAC value back from the LimeSDR, it doesn’t handle writing to the DAC.
See here for how to process the incoming DAC value from the C++ API and write that to the 7311 DAC.
The pre-built image I have on Github that works with the upgraded DAC has lot’s of other modifications to the gateware (allowing for PPS reporting over USB) so I would advise against using it!
I am a bit puzzled about possible external clock frequencies.
Here, @mc955 was wondering whether only 40MHz would work. @Ralfreported that an external clock at 30.72MHz works just fine. @Zackconfirms that 10MHz is possible (while reducing the NIOS CPU speed to a third). Then, @dchard expresses his disappointment that 10MHz would be infeasible. Now, the LMK00105’s datasheet specifies the input frequency to be 10MHz to 40MHz.
So, am I right to assume that anything from 10MHz to 40MHz is a valid input frequency? Or does the claim of the 10MHz-infeasibility stem from the reduced CPU performance?
The clock doesnt just feed the LMS7002, it also feeds the FPGA’s PLL which is what the NIOS runs on. I believe that is expecting a 40 MHz input and the PLL settings are configured in the gateware so these cant be changed on the fly unlike the LMS7002 PLL settings which can be configure in LimeSuite GUI. I wouldn’t expect the device to function properly (e.g. full performance) with a 10 MHz input, although if your sample rate is low you could get away with it. Personally I would just use a 40 MHz ref.
Just out of curiosity: would it be possible to modify the NIOS slightly, that with a switch in LimeSuite this modification can be done? So for example you can select the 40MHz default config, and a 10MHz external clock config which changes the relevant PLL settings as well? I think we can all agree that without this the clock input is virtually useless to a lot of us…
My main disappointment is that the product spec. is very misleading in this regard. Indicating that an external clock ref is possible, but not specifying that it only accepts 40MHz, and even for that you need to hardware hack (=loose warranty) the device, is quite an important info, and I still urge Lime to add this to the Mini’s tech spec.
