Greetings,
I have a question regarding the proper utilization of MIMO for the XTRX v1.2 module.
My goal is to test algorithms that require phase alignment between receiving channels A and B.
I understand that MIMO phase alignment was available for the LMS7002M in the older version of LimeSuite. However, it seems this feature is not yet implemented in LimeSuiteNG. While there is a parameter in the StreamingConfig structure intended for this purpose, it appears to be unused during the LimeSDR_XTRX::StreamCreate and TRXLooper::Setup calls.
I attempted to reimplement the sequence described in the LimeSDR USB MIMO channel alignment reference manual and created a patch. Most changes were made in the TRXLooper class, with minor adjustments to LMS7002.h. Now, AlignRxRF is called whenever the StreamConfig.alignPhase parameter is set to true during the TRXLooper::Start() procedure.
However, my implementation for reading samples is flawed. I start the stream from the FPGA using fpga->StartStreaming(), set mStreamEnable = true to activate the ReceiveLoop, and call StreamRx to get the samples.
Here is what I have:
diff --git a/src/include/limesuiteng/LMS7002M.h b/src/include/limesuiteng/LMS7002M.h
index 96823354..20f393d7 100644
--- a/src/include/limesuiteng/LMS7002M.h
+++ b/src/include/limesuiteng/LMS7002M.h
@@ -853,8 +853,6 @@ class LIME_API LMS7002M
LMS7002M::Channel mStoredValue; ///< The channel to restore to
bool mNeedsRestore; ///< Whether the channel needs restoring or not
};
-
- private:
///enumeration to indicate module registers intervals
enum class MemorySection : uint8_t {
LimeLight = 0,
@@ -900,6 +898,7 @@ class LIME_API LMS7002M
LMS7002M_RegistersMap* BackupRegisterMap();
void RestoreRegisterMap(LMS7002M_RegistersMap* backup);
+ private:
CGENChangeCallbackType mCallback_onCGENChange;
void* mCallback_onCGENChange_userData;
diff --git a/src/streaming/TRXLooper.cpp b/src/streaming/TRXLooper.cpp
index 5122eb48..a6cfc19e 100644
--- a/src/streaming/TRXLooper.cpp
+++ b/src/streaming/TRXLooper.cpp
@@ -206,6 +206,19 @@ OpStatus TRXLooper::Start()
mRx.terminate.store(false, std::memory_order_relaxed);
mTx.terminate.store(false, std::memory_order_relaxed);
+ if (mConfig.alignPhase)
+ {
+ lime::info("Channel Alignement started");
+ AlignRxRF();
+ lime::info("Channel Alignement completed");
+
+ fpga->StopStreaming();
+ fpga->StopWaveformPlayback();
+ fpga->ResetPacketCounters(chipId);
+ fpga->ResetTimestamp();
+ mStreamEnabled = false;
+ }
+
fpga->StartStreaming();
{
std::lock_guard<std::mutex> lock(streamMutex);
@@ -317,6 +330,306 @@ void TRXLooper::Teardown()
TxTeardown();
}
+void TRXLooper::AlignRxRF()
+{
+ uint32_t reg20 = lms->SPI_read(0x20);
+ auto regBackup = lms->BackupRegisterMap();
+ lms->SPI_write(0x20, 0xFFFF);
+ lms->SetDefaults(LMS7002M::MemorySection::RFE);
+ lms->SetDefaults(LMS7002M::MemorySection::RBB);
+ lms->SetDefaults(LMS7002M::MemorySection::TBB);
+ lms->SetDefaults(LMS7002M::MemorySection::TRF);
+ lms->SPI_write(0x10C, 0x88C5);
+ lms->SPI_write(0x10D, 0x0117);
+ lms->SPI_write(0x113, 0x024A);
+ lms->SPI_write(0x118, 0x418C);
+ lms->SPI_write(0x100, 0x4039);
+ lms->SPI_write(0x101, 0x7801);
+ lms->SPI_write(0x103, 0x0612);
+ lms->SPI_write(0x108, 0x318C);
+ lms->SPI_write(0x082, 0x8001);
+ lms->SPI_write(0x200, 0x008D);
+ lms->SPI_write(0x208, 0x01FB);
+ lms->SPI_write(0x400, 0x8081);
+ lms->SPI_write(0x40C, 0x01FF);
+ lms->SPI_write(0x404, 0x0006);
+ lms->LoadDC_REG_IQ(TRXDir::Tx, 0x3FFF, 0x3FFF);
+
+ double srate = lms->GetSampleRate(TRXDir::Rx, LMS7002M::Channel::ChA);
+ lms->SetFrequencySX(TRXDir::Rx, 450e6);
+ int dec = lms->Get_SPI_Reg_bits(LMS7002MCSR::HBD_OVR_RXTSP);
+ if (dec > 4) dec = 0;
+
+ double offsets[] = {1.15/60.0, 1.1/40.0, 0.55/20.0, 0.2/10.0, 0.18/5.0};
+ double tolerance[] = {0.9, 0.45, 0.25, 0.14, 0.06};
+ double offset = offsets[dec]*srate/1e6;
+ std::vector<uint32_t> dataWr(16);
+
+ fpga->WriteRegister(0xFFFF, 1 << chipId);
+ fpga->StopStreaming();
+ mStreamEnabled = false;
+ fpga->WriteRegister(0x0008, 0x0100);
+ fpga->WriteRegister(0x0007, 3);
+ bool found = false;
+ for (int i = 0; i < 200; i++){
+ lms->Modify_SPI_Reg_bits(LMS7002MCSR::PD_FDIV_O_CGEN, 1);
+ lms->Modify_SPI_Reg_bits(LMS7002MCSR::PD_FDIV_O_CGEN, 0);
+ AlignRxTSP();
+
+ lms->SetFrequencySX(TRXDir::Tx, 450e6+srate/16.0);
+ double offset1 = GetPhaseOffset(32);
+ lime::info("Phase offset1 %lf", offset1);
+ if (offset1 < -360)
+ break;
+ lms->SetFrequencySX(TRXDir::Tx, 450e6+srate/8.0);
+ double offset2 = GetPhaseOffset(64);
+ lime::info("Offset 1: %lf 2: %lf", offset1, offset2);
+ if (offset2 < -360)
+ break;
+ double diff = offset1-offset2;
+ lime::info("Diff %lf, offset %lf, tolerance %lf decimation %d", diff, offset, tolerance[dec], dec);
+ if (abs(diff-offset) < tolerance[dec])
+ {
+ found = true;
+ break;
+ }
+ }
+
+ lms->RestoreRegisterMap(regBackup);
+ if (found)
+ AlignQuadrature();
+ else
+ lime::warning("Channel alignment failed base offset not found.");
+ lms->SPI_write(0x20, reg20);
+}
+
+double TRXLooper::GetPhaseOffset(uint32_t bin)
+{
+ StreamMeta meta;
+ uint32_t count;
+
+ complex32f_t** rxSamples = new complex32f_t*[2];
+ for (int i = 0; i < 2; ++i)
+ {
+ rxSamples[i] = new complex32f_t[2 * bin];
+ }
+
+ fpga->StartStreaming();
+ mStreamEnabled = true;
+ count = StreamRx(rxSamples, 2 * bin, &meta, std::chrono::milliseconds(1000));
+
+ if (count != 2 * bin)
+ {
+ lime::warning("Channel alignment failed: GetPhaseOffset can't read from FIFO %u", count);
+ return -1000;
+ }
+
+ fpga->StopStreaming();
+ mStreamEnabled = false;
+
+ //calculate DFT bin of interest and check channel phase difference
+ const std::complex<double> iunit(0, 1);
+ const double pi = std::acos(-1);
+ const int N = 512;
+ std::complex<double> xA(0, 0);
+ std::complex<double> xB(0, 0);
+ for (int n = 0; n < N; n++)
+ {
+ const std::complex<double> xAn(rxSamples[0][n].real(), rxSamples[0][n].imag());
+ const std::complex<double> xBn(rxSamples[1][n].real(), rxSamples[1][n].imag());
+ const std::complex<double> mult = std::exp(-2.0 * iunit * pi * double(bin) * double(n) / double(N));
+ xA += xAn * mult;
+ xB += xBn * mult;
+ }
+ double phaseA = std::arg(xA) * 180.0 / pi;
+ double phaseB = std::arg(xB) * 180.0 / pi;
+ double phasediff = phaseB - phaseA;
+ if (phasediff < -180.0) phasediff +=360.0;
+ if (phasediff > 180.0) phasediff -=360.0;
+
+ for (int i = 0; i < 2; ++i)
+ delete[] rxSamples[i];
+ delete[] rxSamples;
+
+ return phasediff;
+}
+
+void TRXLooper::RstRxIQGen()
+{
+ uint32_t data[16];
+ uint32_t reg20;
+ uint32_t reg11C;
+ uint32_t reg10C;
+ data[0] = (uint32_t(0x0020) << 16);
+ fpga->ReadLMS7002MSPI(data, ®20, 1);
+ data[0] = (uint32_t(0x010C) << 16);
+ fpga->ReadLMS7002MSPI(data, ®10C, 1);
+ data[0] = (1 << 31) | (uint32_t(0x0020) << 16) | 0xFFFD;
+ fpga->WriteLMS7002MSPI(data, 1);
+ data[0] = (uint32_t(0x011C) << 16);
+ fpga->ReadLMS7002MSPI(data, ®11C, 1);
+ data[0] = (1 << 31) | (uint32_t(0x0020) << 16) | 0xFFFD; //SXR
+ data[1] = (1 << 31) | (uint32_t(0x011C) << 16) | (reg11C | 0x10); //PD_FDIV
+ data[2] = (1 << 31) | (uint32_t(0x0020) << 16) | 0xFFFF; // mac 3 - both channels
+ data[3] = (1 << 31) | (uint32_t(0x0124) << 16) | 0x001F; //direct control of powerdowns
+ data[4] = (1 << 31) | (uint32_t(0x010C) << 16) | (reg10C | 0x8); // PD_QGEN_RFE
+ data[5] = (1 << 31) | (uint32_t(0x010C) << 16) | reg10C; //restore value
+ data[6] = (1 << 31) | (uint32_t(0x0020) << 16) | 0xFFFD; //SXR
+ data[7] = (1 << 31) | (uint32_t(0x011C) << 16) | reg11C; //restore value
+ data[8] = (1 << 31) | (uint32_t(0x0020) << 16) | reg20; //restore value
+ fpga->WriteLMS7002MSPI(data, 9);
+}
+
+void TRXLooper::AlignRxTSP()
+{
+ uint32_t reg20;
+ uint32_t regsA[2];
+ uint32_t regsB[2];
+ //backup values
+ {
+ const std::vector<uint32_t> bakAddr = { (uint32_t(0x0400) << 16), (uint32_t(0x040C) << 16) };
+ uint32_t data = (uint32_t(0x0020) << 16);
+ fpga->ReadLMS7002MSPI(&data, ®20, 1);
+ data = (uint32_t(0x0020) << 16) | 0xFFFD;
+ fpga->WriteLMS7002MSPI(&data, 1);
+ fpga->ReadLMS7002MSPI(bakAddr.data(), regsA, bakAddr.size());
+ data = (uint32_t(0x0020) << 16) | 0xFFFE;
+ fpga->WriteLMS7002MSPI(&data, 1);
+ fpga->ReadLMS7002MSPI(bakAddr.data(), regsB, bakAddr.size());
+ }
+
+ //alignment search
+ {
+ uint32_t dataWr[4];
+ uint32_t count;
+ StreamMeta meta;
+
+ complex32f_t** rxSamples = new complex32f_t*[2];
+ for (int i = 0; i < 2; ++i)
+ {
+ rxSamples[i] = new complex32f_t[64];
+ }
+
+ dataWr[0] = (1 << 31) | (uint32_t(0x0020) << 16) | 0xFFFF;
+ dataWr[1] = (1 << 31) | (uint32_t(0x0400) << 16) | 0x8085;
+ dataWr[2] = (1 << 31) | (uint32_t(0x040C) << 16) | 0x01FF;
+ fpga->WriteLMS7002MSPI(dataWr, 3);
+
+ fpga->StopStreaming();
+ mStreamEnabled = false;
+ fpga->WriteRegister(0xFFFF, 1 << chipId);
+ fpga->WriteRegister(0x0008, 0x0100);
+ fpga->WriteRegister(0x0007, 3);
+
+ dataWr[0] = (1 << 31) | (uint32_t(0x0020) << 16) | 0x55FE;
+ dataWr[1] = (1 << 31) | (uint32_t(0x0020) << 16) | 0xFFFD;
+
+ for (int i = 0; i < 100; i++)
+ {
+ fpga->WriteLMS7002MSPI(&dataWr[0], 2);
+
+ fpga->StartStreaming();
+ mStreamEnabled = true;
+ count = StreamRx(rxSamples, 64, &meta, std::chrono::milliseconds(1000));
+
+ if (count != 64)
+ {
+ lime::warning("Channel alignment failed : AlignRxTSP cannot read from FIFO %u", count);
+ break;
+ }
+ fpga->StopStreaming();
+ mStreamEnabled = false;
+
+ if (rxSamples[0][0].real() == rxSamples[1][0].real() && rxSamples[0][0].imag() == rxSamples[1][0].imag())
+ break;
+ }
+
+ for (int i = 0; i < 2; ++i)
+ delete[] rxSamples[i];
+ delete[] rxSamples;
+ }
+
+ //restore values
+ {
+ uint32_t dataWr[7];
+ dataWr[0] = (uint32_t(0x0020) << 16) | 0xFFFD;
+ dataWr[1] = (uint32_t(0x0400) << 16) | regsA[0];
+ dataWr[2] = (uint32_t(0x040C) << 16) | regsA[1];
+ dataWr[3] = (uint32_t(0x0020) << 16) | 0xFFFE;
+ dataWr[4] = (uint32_t(0x0400) << 16) | regsB[0];
+ dataWr[5] = (uint32_t(0x040C) << 16) | regsB[1];
+ dataWr[6] = (uint32_t(0x0020) << 16) | reg20;
+ fpga->WriteLMS7002MSPI(dataWr, 7);
+ }
+}
+
+void TRXLooper::AlignQuadrature()
+{
+ auto regBackup = lms->BackupRegisterMap();
+
+ lms->SPI_write(0x20, 0xFFFF);
+ lms->SetDefaults(LMS7002M::MemorySection::RBB);
+ lms->SetDefaults(LMS7002M::MemorySection::TBB);
+ lms->SetDefaults(LMS7002M::MemorySection::TRF);
+ lms->SPI_write(0x113, 0x0046);
+ lms->SPI_write(0x118, 0x418C);
+ lms->SPI_write(0x100, 0x4039);
+ lms->SPI_write(0x101, 0x7801);
+ lms->SPI_write(0x108, 0x318C);
+ lms->SPI_write(0x082, 0x8001);
+ lms->SPI_write(0x200, 0x008D);
+ lms->SPI_write(0x208, 0x01FB);
+ lms->SPI_write(0x400, 0x8081);
+ lms->SPI_write(0x40C, 0x01FF);
+ lms->SPI_write(0x404, 0x0006);
+
+ lms->LoadDC_REG_IQ(TRXDir::Tx, 0x3FFF, 0x3FFF);
+ lms->SPI_write(0x20, 0xFFFE);
+ lms->SPI_write(0x105, 0x0006);
+ lms->SPI_write(0x100, 0x4038);
+ lms->SPI_write(0x113, 0x007F);
+ lms->SPI_write(0x119, 0x529B);
+ auto val = lms->Get_SPI_Reg_bits(LMS7002MCSR::SEL_PATH_RFE, true);
+ lms->SPI_write(0x10D, val==3 ? 0x18F : val==2 ? 0x117 : 0x08F);
+ lms->SPI_write(0x10C, val==2 ? 0x88C5 : 0x88A5);
+ lms->SPI_write(0x20, 0xFFFD);
+ lms->SPI_write(0x103, val==2 ? 0x612 : 0xA12);
+ val = lms->Get_SPI_Reg_bits(LMS7002MCSR::SEL_PATH_RFE, true);
+ lms->SPI_write(0x10D, val==3 ? 0x18F : val==2 ? 0x117 : 0x08F);
+ lms->SPI_write(0x10C, val==2 ? 0x88C5 : 0x88A5);
+ lms->SPI_write(0x119, 0x5293);
+
+ double srate = lms->GetSampleRate(TRXDir::Rx, LMS7002M::Channel::ChA);
+ double freq = lms->GetFrequencySX(TRXDir::Rx);
+
+ lms->SPI_write(0xFFFF, 1 << chipId);
+ fpga->StopStreaming();
+ mStreamEnabled = false;
+ lms->SPI_write(0x0008, 0x0100);
+ lms->SPI_write(0x0007, 3);
+ lms->SetFrequencySX(TRXDir::Tx, freq+srate/16.0);
+
+ bool found = false;
+ for (int i = 0; i < 100; i++){
+
+ double offset = GetPhaseOffset(32);
+ lime::info("Phase offset3 %lf", offset);
+ if (offset < -360)
+ break;
+ if (fabs(offset) <= 90.0)
+ {
+ found = true;
+ break;
+ }
+ RstRxIQGen();
+ }
+
+ lms->RestoreRegisterMap(regBackup);
+ if (!found)
+ lime::warning("Quadrature Channel alignment failed");
+
+}
+
OpStatus TRXLooper::RxSetup()
{
OpStatus status = mRxArgs.dma->Initialize();
diff --git a/src/streaming/TRXLooper.h b/src/streaming/TRXLooper.h
index ee1a108c..5d53bc57 100644
--- a/src/streaming/TRXLooper.h
+++ b/src/streaming/TRXLooper.h
@@ -85,6 +85,12 @@ class TRXLooper : public RFStream
};
private:
+ void AlignRxRF();
+ double GetPhaseOffset(uint32_t bin);
+ void RstRxIQGen();
+ void AlignRxTSP();
+ void AlignQuadrature();
+
OpStatus RxSetup();
void RxWorkLoop();
void ReceivePacketsLoop();
For now, the calibration is always failing during the 200 iterations in AlignRxRF(). The absolute phase offset never lies near the tolerance.
My questions are:
- Is it still the correct approach to perform phase alignment on the XTRX?
- If so, should I use the
StreamRxmethod to recover the IQ samples inGetPhaseOffset,AlignRxTSP, andAlignQuadrature? What would be a better way to do so?
Thank you.