Glad to find this community.
By using GNU Radio and RTL-SDR, we were able to decode a Digital Mobile Radio (DMR) signal and play it back. The GNU Radio tool that perform is called DMR Speech Decoder (DSD).
Unfortunately, that doesn’t work when we replaced the RTL-SDR with our system that has Altera SoC and UNITE7002.
Given that, our system is able to show FFT, Waterfall, Tx/Rx to/from another system and decoding the commercial FM stations.
We are running out of time and we are looking for support and consultation on this issue, so if you think you can get it solved please advice me or contact me on: fahad.almalki@itsec360.com
So, is there any thing we are missing? not configuring properly?
Hi @Fahad, STREAM + LMS7002M EVB was the original reference platform for Lime Suite, but this subsequently changed to LimeSDR and at this point in time I’m not sure what the status of support is for that combination. May be that updated FPGA and/or FX3 images are needed. Tagging @joshblum and @Zack, as they may know.
That said, it sounds like you’re maybe using SoapySDR / UHD / gr-osmosdr for other stuff? If so, not sure why those apps would work but not DMR, if that works fine with humble RTL-SDR hardware…
Thanks for your reply.
UNITE7002 is interfaced to our Altera SoC Dev Board via LimeLight interface, and we are using J7 pins.
The samples then are transmitted from the SoC to the GNU Radio via the network, and GNU Radio receives them from TCP Source block.
Exactly, so could you please advice me about this issue, or may be forwarding me to someone who might helps.
CC to the gents @joshblum & @Zack
Is there any chance to get interconnection schematic between your board and UNITE7002?
Another question - UNITE7002 got buffers on LimeLight bus interface. Are you sure you drive it properly?
By the way, could you identify your board, please. There should be a sticker on the bottom of the board.
Another question - how do you power UNITE7 board?
Thanks for your reply.
Basically we are connecting the pins from J7 as following:
LMS J7 __________________ Altera SoC
IQSELEN2RX ------------------- Input GPIO PIN
MCLK2RX------------------------ Input GPIO PIN
DIQ2TX BUS -------------------- 12-pin input GPIO BUS
IQSELEN1TX ------------------- Output GPIO PIN
FCLK1TX ------------------------ Output GPIO PIN
DIQ1RX BUS ------------------- 12-pin output GPIO BUS
SDIO ----------------------------- MOSI
SDO ------------------------------ Oscilloscope
SCLK ----------------------------- SPICLK
CS_ ------------------------------- CS_
(Sometimes we keep CS_ connected to the ground to force it working all the time, do you think that will make it more reliable?)
