TXCLK / RXCLK Zipper Board

Has anyone ever tried Developing An RF system with using the:

Zipper + Zed board + Myriad RF.

Whoever designed the Zipper seems that he never tried to do this.

The TX and RX clock coming from the SI5351C are routed through the FMC to the Zynq on the Zedbaord yet they routed it to pins that are not Clock capable. From the schematic the TX clock is connected to H11 and RX clock connected to H07. If you follow the connection through the zedboard it connects to IO_L14N_T2_DQS and IO_L20P_T3.

Has anyone else found this issue and a work around?

I need the Clock’s generated by the SI chip to run my TX Dac IQ algorithm in the FPGA.

Maybe I will have to jumper FMC pins to get the Clocks on Clock capable pins for the Zynq. This is not ideal.

Let me know if anyone else has any ideas.

I currently have a project with HDL and Software that configured the SI CLK 0 CLK2, CLK3, CLK4, CLK5 and software that communicates with the LMS spi. But I need to be changing the I/Q DAC of the lime at the rate of the TX clk and RX clk or else metastability issues will occur. I need the clock routed into the ZYNQ and used by my custom IP to setup the TX dac and receive adc data on the RX ADC.


What if:

On the Zipper board I Removed R84, R86, R87, R89 and connected R85 and R88. This would route the FMC TX clock pin directly to the Lime TX clock pin. Then I could use the Zedboard’s onboard 100 Mhz run it through a clock manager to get 80 MHz and output on the TX_CLK_C pin. Also I would do that for the RX_CLK_C as well.

I am going to try this.