That would be great. I spent some more time looking at the VHDL, and I think I’m starting to see why it doesn’t work. There are two timers keeping track of the sample number - one appears to count the samples as they are received from the LMS7002M, the other appears to count them as they get loaded into packets. It looks to me like the former runs regularly, but the second is bursty. So they both get reset at the same time, but they didn’t necessarily have the same values when they were reset.
I’m working on a new plan - instead of resetting the sample count, I’ll try to report the time that the GPIO goes from L->H. When the GPIO is high, the time value that gets reported in the rx packet header will be the stored time from the timer that counts incoming samples. So that receiving software can tell the difference, I flip on the highest bit in the time word. At this point this strategy is functional, still need to test if it gives good synchronization.
I’m a complete novice at vhdl, so my interpretation of what’s going on in here should certainly be read with appropriate caution.