I am working to use GPIO0 as a synchronization input as described in the following thread: Synchronize two LimeSDR - #44 by cmichal
This uses the pin to modify the HW timestamps when a sync pulse occurs.
The FPGA modifications worked until about three weeks ago, and I think it may be due to a GPIO input hardware issue. When I apply any external input to the GPIO pins, the value read on the pin toggles between Low and High. This occurs whether I supply a constant logic 1 or a logic 0 to the pin. If there is nothing connected to the pin it always reads logic High. This appears to occur for all of the FPGA GPIO pins. Here is a graph I made of the read measurements on GPIO0 when constant logic High is applied.
I’ve never seen anything like that. It would certainly help diagnose it if
you had a second board available to test. But, before spending more money, it might make sense to double check that the firmware and library versions are known to work together - you didn’t by chance update LimeSuite or some other software component?
Thank you for your quick reply! I have not updated LimeSuite or another software component. This is for a Senior capstone project, and we have 3 LimeSDR’s split up among our team. I will borrow a one of the other boards later today and see if the issue still occurs.
RESOLVED:
It turns out that when I ran some sample code from LimeSuite for the GPIO pins it set many of the pins as an output. I didn’t re-set the GPIO pins as input when I tested the FPGA mod. When the pins are set as input everything works as it should.
