I am working to use GPIO0 as a synchronization input as described in the following thread: Synchronize two LimeSDR
This uses the pin to modify the HW timestamps when a sync pulse occurs.
The FPGA modifications worked until about three weeks ago, and I think it may be due to a GPIO input hardware issue. When I apply any external input to the GPIO pins, the value read on the pin toggles between Low and High. This occurs whether I supply a constant logic 1 or a logic 0 to the pin. If there is nothing connected to the pin it always reads logic High. This appears to occur for all of the FPGA GPIO pins. Here is a graph I made of the read measurements on GPIO0 when constant logic High is applied.
This issue occurs for both the modified and the standard up to date FPGA gateware. LimeQuickTest passes for both.
Does this issue sound like a physical problem with the GPIO pins? Is it necessary for me to purchase a new LimeSDR to get this working?
What is the best way to debug issues with the GPIO pins, it does not appear like this is included in LimeQuickTest?
Thank you,
Josh