ok, I think we’re mostly after the same thing here. I would hope to get to the point where the synchronization between boards is a small fraction of a sample dwell. As far as phase synchronization of the actual rf signals themselves on different boards - I don’t much care. I’m generally working at different frequencies on different boards and their phase coherence doesn’t matter. I need the timing of the timestamps to be accurately known though.
For you its true - I think you will always have a phase issue amongst the rf signals on multiple boards. I don’t know any way around that.
I spent a little more time looking at how the ADC and DAC sample clocks are generated, and syncing them between multiple boards looks tricky. I think I do see a path to doing it, but that may be just naive optimism from someone who doesn’t know enough about fpgas to know better.
The DAC and ADC clocks both come from the divided down CGEN VCO. The barrier in my mind is syncing the divisors. The CGEN PLL seems to have two possibly relevant signals: RESET_N_SYNC and PD_FDIV_O_CGEN. The former sounds like it might be just the ticket, though it seems to reset quite a few pieces of the PLL, and I wonder if that means that the loop would drop out of lock? And if so would it lock again with the same timing on all boards necessarily?
The PD_FDIC_O_CGEN just powers down the divider, presumably leaving the VCO locked. Perhaps if you powered the divider down on all the boards and powered them back up simultaneously they’d all be in sync.
Unfortunately both of those signals are bits in registers in the LMS7002M, accessed by SPI, and not obviously easy to toggle from the FPGA. Perhaps one could have a module in the FPGA that, when triggered externally by GPIO, hijacked the SPI interface and bit-banged the instructions to toggle the RESET_N_SYNC line or the divider power? Unfortunately, this looks to be somewhat (ie, way) beyond my ability - but I’d be very interested in having it work.
One thing that I could conceivably try though, is doing this in software with very low sample rates. If the sample rate could be brought down to say 1kHz or so, then toggling those registers with the existing mechanisms seems likely to tell whether this strategy is worth pursing.
Are you working on CHIME? If so, it seems likely we know some people in common.