SRS-RAN and XTRX

As XTRX is another LMS7002M based SDR, and as it seems we are having low level issues with the device, and the development ceased to exist for a long time now, I decided to open a topic here, maybe @Zack or @andrewback can shed some light on the internals of the TBB (filtering and path selection), as that is where we suspect the issue is.

First of all, the XTRX supported SRS-RAN version can be found here: GitHub - arun1969/srsRAN: Open source SDR 4G/5G software suite from Software Radio Systems (SRS)

Most of the development effort and findings are here: Support of srsLTE · Issue #68 · xtrx-sdr/images · GitHub

The short summary is that at the moment, we are having spectrum flatness issues when 5 and 10MHz LTE signal is generated, and filtering + high noise issues on 15 and 20MHz.

This is a 5MHz LTE DL signal with vector analysis and no equalization:

This is a 10MHz LTE DL signal with vector analysis and no equalization:

In both cases the spectrum flatness issue is quite visible.

This is the spectrum analysis of the later (10MHz signal):

Our prime suspect is somewhere in the TBB, more precisely somewhere in the filter settings, as if we force the signal to high path the spectrum flatness issue is gone, but in this case we see massive noise floor increase (barely 10dB difference between the noise floor and actual signal level).

I know this is not closely on topic here, but as it looks like a low level issue around the LMS7002M, hopefully someone can help us.

I’ve asked a colleague if they could take a look and offer any advice. Obviously we’re not so familiar with third party hardware which uses our silicon.

Occurred to me also that there may possibly be some useful clues in the experimental fork of srsLTE that we created some time ago, which has native LMS API integration.

Hi Andrew,

Yes, every bit of help is much appreciated. Thank you for that.

The issue is, that XTRX uses their own LMS driver you can find it here

It has some level of DC correction, but no TX or RX calibration at all, as much as I can see it. Not sure if that can create something like this. The quite coherent and symmetrical “triangle” shape o the spectrum indicates a filter setting issue. And as much as I understand, only analog filters are at play in our case.

If you or any of your colleagues can at least point us towards an area which might cause something like this, we can modify the XTRX LMS driver to print or hack in whatever registers that needs change. I checked the CGIAMP and RCAL_LPFH_TBB settings (even manually calculated them for a given LTE bandwidth), but I dont think those are the ones causing this.

MOD: the other question I had is timing, or timing calibration:

When I force the LTE signal to high path, the signal is good enough for a phone to lock on to it, the first random access is sent by the phone, which was never received/detected by the SRS enodeb. This can be a lot of things (RX path, gain, filter etc.) but I would say without any timing calibration, the likely culprit might be that.

How can we do a timing cal to be sure that the enb received the uplink signal when it expects it?

@andrewback @Zack

I did a couple checks with a LimeSDR-Mini, and it seems something is not right with that as well.

This is a 5MHz signal:

This is a 10MHz signal:

Previously I only did vector analysis with LimeSDR-Mini and that was fine as the instrument bandwidth was set to the channel bandwidth, so the wider area of the edges was not visible.

My question is: is this how it supposed to look, or some filter settings are really incorrect here? Would be nice to establish a baseline with LimeSDR-Mini so we know what we are aiming for. The above outputs were generated by SRS-RAN via Soapy.

Hi @dchard ,

Could you please perform LimeQuictTest and share log file.

Hi Zack,

I am abroad atm, will get back to you on wendesday. Thanks for your help in advance!

I hope this is what you needed, during the quick test, both TX and RX ports were open. During vector analysis, I often terminate the RX port to a 50 OHm (wideband) load, while the TX port is connected to the VSA. Dont think this is relevant, but I wanted to share every detail.

[ TESTING STARTED ]
->Start time: Tue Mar 15 16:14:28 2022
->LimeSuite version: 20.10.0-g67edf073

->Device: LimeSDR Mini, media=USB 3.0, module=FT601, addr=24607:1027, serial=1D3AD6D55166A0, HW=1, GW=1.30
  Serial Number: 1D3AD6D55166A0
 Chip temperature: 30 C

[ Clock Network Test ]
->REF clock test
  Test results: 50404; 63601; 11262 - PASSED
->VCTCXO test
  Results : 6710952 (min); 6711116 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 00 00 00 12 02 18 02
->FPGA EEPROM Test FAILED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
  Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
  Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
->Configure LMS
->Run Tests (TX_2 -> LNA_W):
  CH0 (SXR=1000.0MHz, SXT=1005.0MHz): Result:(-17.0 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_H):
  CH0 (SXR=2100.0MHz, SXT=2105.0MHz): Result:(-16.7 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test PASSED

=> Board tests FAILED <=

Elapsed time: 2.75 seconds

@Zack Did you have time to look at it by any chance?

@Zack let me try again. Hope you had some time for this.