RX IQ select poliarity/timing

Projects Reference Development Kit
1

I tried to understand the timing of the IQ Sel signal and it’s relation to data.

The relevant doc I looked at are

  • Programming manual - Table 13 - Description of register 0x5a bit 7
  • Datasheet - Figure 8, Figure 11 and Figure 12.

Now there are several things that are not clear in the doc :

  • The Table 13 says the RX fsync polarity bit can be ‘0’ or ‘1’ but doesn’t say which one correspond to ‘positive polarity’ and ‘negative polarity’ as described in Figure 8.

  • I assume Figure 12 shows the timing for the ‘default’ configuration ?

  • Figure 11 logic and Figure 12 don’t seem to match. First the I_DATA/Q_DATA should take one RX_CLK cycle before being on RXD since there is a register.
    Further more, if you plug the ‘0’ / ‘1’ bits from the config registers into figure 11 diagram and try to work out the output (assuming that the mux output ‘A’ is for ‘0’ and ‘B’ for ‘1’), then it doesn’t seem to match, the fsync polarity seem to be reversed.

    For example, let’s assume the default settings ( adc_clk_pol = ‘rising edge’, rx_interleave_mode = ‘0’ (I/Q), rx_fsync_polarity = ‘0’ ).
    We should get something like this : http://i.imgur.com/LwSQ3Vg.png

    But that doesn’t seem to match Figure 12 (which I think should be the default config) and more importantly, that doesn’t seem to be what we observe.

So, could you clear up the doc a bit ?