We are interested in knowing if there is a way to setup the LMS6002 chip to generate a deterministic pattern on the I and Q bits in order to verify our sampling and capture timing parameters and synthesis constraints.
I was hoping to learn from your design, but I notice that you have not implemented the RX side. You are welcome to use the one we developed, and we are happy to collaborate with you on it.
It is great to see that you have developed the RX interface using Lattice. We are developing the code to capture the RX data via Altera FPGA on the current interface board, the database of which can be obtained from :
We are going to check out your code, thank you for sharing.
You can generate a digital Sine (nco) in FPGA as TX IQ samples and loop back the TX DAC to the RX ADC input and monitor the samples from the ADC for a complete versification of the interface between the FPGA and LMS6002D. You could use the nco VHDL code in:
Thanks for sharing. Would you be willing to do a short piece explaining how you went about doing this and what you can do with it … so others could do the same.
@Andrew, our hardware is setup for digital receive only (we dont have enough pins to send TX data to the LIME). However, we have been working on a way to generate a CW signal using the TX chain in the LIME without feeding it digital data.
You can make use of analog Tx inputs, connecting them to one of Agilent generators with differential I/Q outputs. I could supply you a waveform to drive the generator outputs, if you are interested.
Thanks. We have got an HP 8648C signal generator we use to test/calibrate with. Our interest is in self-calibration of the LMS6002D that can be accomplished without external equipment.
It turns out to be quite a challenge to do it by communicating with the chip directly (not using the GUI provided). There are still a few ‘magic’ codes that we have not found yet.
