RX channels alignment

Projects LimeSDR
10

I don’t have access to exact sources right now. Here are my routines as i remember them.

In limesuite SoapyLMS7/Settings.cpp

unsigned SoapyLMS7::transactSPI(const int addr, const unsigned data, const size_t /*numBits*/)
{
    uint32_t input = data;
    uint32_t readback = 0;
    int st;
	if((addr>>15)&1)//write
		st	= _conn->TransactSPI(addr, &input, 0, 1);
	else
		st	= _conn->TransactSPI(addr, &input, &readback, 1);
	
	
    if (st != 0) throw std::runtime_error(
        "SoapyLMS7::transactSPI("+std::to_string(addr)+") FAIL");
    return readback;
}

In my code

void MyClass::writeReg(int addr, int data){
	device->transactSPI(addr|(1<<15),data,0);
}

int MyClass::readReg(int addr){
	int ret=device->transactSPI(addr,0,0);
	return ret;
}

void MyClass::alignChannels(){
int reg=0;
//1. Disable clock generator, set EN_G_CGEN 0x0086[0]=0
reg=readReg(0x86);
reg&=~(1<<0);
writeReg(0x86,reg);
//2. Reset RxTSP logics by toggling(1->0->1) 0x0020[9] LRST_RX_A, 0x0020[11] LRST_RX_B
reg=readReg(0x20);
reg&=~((1<<9)|(1<<11));
writeReg(0x20,reg);
reg|=((1<<9)|(1<<11));
writeReg(0x20,reg);
//3. Enable clock generator, set EN_G_CGEN 0x0086[0]=1
reg=readReg(0x86);
reg|=(1<<0);
writeReg(0x86,reg);
}

I will post original sources later today. Reading and writting to registers works correctly.