Hello,
Before the first run of LimeSDR I’ve performed a test and everything was ok. After some time i got the RF Loopback Test FAILED.
I’ve checked both TX 1, LNA_W of CH 0 (RX 1_W and TX1_1) and they are both seems working. No any noticeable difference between RX 1_L or TX1_2 for example. But test is still failed.
Could you please advise how this loopback is working? There is no any connection between RX 1_W and TX1_1. I can see there are some connection between TX 1/2_2 and RX 1/2_H on the schematic diagram but only for these two ports. Maybe it’s possible to found a faulty element and to replace it. Of course if it’s not a faulty IC.
Nothing was connected to the board.
Dear LimeSDR team could you please explain how the loopback works and could you please suggest what I can do with this error.
Logs are below:
==========================================================
[ TESTING STARTED ]
->Start time: Sun Jan 26 20:52:11 2020
->Device: LimeSDR-USB, media=USB 3.0, module=FX3, serial=00090726074F2410, index=0
Serial Number: 00090726074F2410
[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 34642; 38398; 42154 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112962 (min); 5113093 (max) - PASSED
->Clock Network Test PASSED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 07 19 12 07 19 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED
[ RF Loopback Test ]
Note: The test should be run without anything connected to RF ports
->Configure LMS
->Run Tests (TX_2-> LNA_L):
CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-14.3 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-16.4 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-22.0 dBFS, 5.00 MHz) - FAILED
CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-17.3 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_2-> LNA_H):
CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-16.0 dBFS, 5.00 MHz) - PASSED
CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-13.7 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test FAILED
=> Board tests FAILED <=
Elapsed time: 1.73 seconds
Thanks in advance.