Thank you very much for your reply. Had a look at the mPCIe edge connector pin definition in Table 16, it seems to be a standard 1x lane mPCIe pin arrangement. Do I miss anything here? Could you please help me on the 2 lanes wiring aspect?
There are PCI_TX1_N, PCI_TX1_P, PCI_RX1_N, and PCI_RX1_P on pins 39, 41, 47, and 49. I think those are not very standard, but are used on some of the embedded systems.
I am considering connecting it with a computer board with a mPCIe interface for I Q sample streaming at around 120MB/s. Is there any tricky aspect I need to pay attention to?
I think you should be fine with a single PCIe lane for 120MB/s, as a single gen2 lane supports 500MB/s (in each direction).
There are some numbers Ricardas mentioned in this post: Some tech questions about the LimeSDR XTRX ecosystem - #3 by ricardas