Register write/read test fails on Zipper and Myriad-RF board development

The hardware setup used:

  • Xilinx Kintex HW-KC705 REV 1.1
  • Installed the Zipper and Myriad-RF board on the FMC LPC connector
  • Used the mini USB connector and software driver with GUI to configure the board.
    The driver is installed and the port is recognized but the “Register Test” invoked from the GUI fails. All register reads returns 00.
    I have the driver 6002Dr2 Control Software Version 2.4.1686.8239
    I tried also unsuccessfully to use the Zipper board in stand alone mode. Removed it from the FMC connector and provided +5V on the J5 Zipper board. It is possible the board is damaged since it takes high current. Measured very low impedance (almost short) on the J5 pins. While I am waiting for a replacement what are your recommendations?

Hello reazvan,

Have you used correct COM port to comunicate with Zipper board. You can check this under Device Manager/Ports by plunging/unplugging USDB cable from Zipper board.3


Hi Andrew,
The COM port is recognized as I plug/unplug the USB. I have the correct port number since the terminal displays the register test results which is all 00. When I don’t have the port set correctly the register test don’t display anything. We found the board is defective and I am sending it back. The quicker fix for us is to order a new Zipper Myriad board development kit. Can I get refund or credit for the defective one which I am sending back?

Hello Razvan,

It is something unusual. Which supplier you’re using?


Hi Andrew,
The supplier is DigiKey. We ordered a new Zipper board.
We’ll use the board at 40MHz for RXCLK/TXCLK in streamline mode. Several Questions:

  • It looks like the MAX frequency setup for the RXCLK/TXCLK is 40MHz (for a data conversion rate of 20MHz); correct? So, that is the upper linit.
  • Is the RXCLK isochronous to the TXCLK? Both signals are provided on the FMC into my application and I want to use a unique clock reference generated from RXCLK for my design. What is the phase relationship of the two? I am asking this since a buffering scheme (FIFOs) suggested into one of the reference designs wouldn’t work in a continuous streamline application; any recommendations or reference designs?
  • Where is located the latest documentation/driver/ref-design for the Zipper and Myriad-RF board?

Thank you.


The maximum TXCLK/RXCLK clock frequency is 80MHz, which gives you 40MHz conversion rate. These pins are asynchronous and separate clocks can be provided for the TXCLK and RXCLK interface. So basically, the digital interface configuration is defined by application needs.

You also can configure the Zipper board and Myriad board so that RXCLK and TXCLK will be provided from your baseband board with different frequencies.

The LMS6002D datasheet you can get from this [link]

All documents related to zipper board you can get from this [link]

GUI in this [link]

Thank you Andrew.

Hi Andrew,
I understand that TXCLK and RXCLK clocks can be set separately from the GUI application on the Zipper or provided from the application board.
My question is, if the same frequency value is set for both clocks TXCLK/RXCLK, from the Zipper GUI, can I assume both clocks are driven from the same PLL? It looks like the Si5351C can generate any frequency up to 160 MHz (or as I need it, same frequency) on each of its outputs with 0 ppm error.
Therefore both clocks could be Isochronous and I should be able to do continuous streamline loop-back on my application board as a simple design case. Correct?
If that is not the case, please point me in the right direction (documentation, working instructions or reference design) so I can guarantee continuous (not buffered, burst) streamline loop-back on the application board.
Thanks again for your help.

Hello Razvan,
The synthesiser (Si5351C) is driven by the Rakon oscillator (TVCXO 30.72MHz). Using GUI you can generate the any clock for TxCLK nad RXCLK. You will need to do one modification on Myriad RF board in order to make it work: make No Fit to R26 and R27 on MyriadRF board.

When this is set up, you could do the continuous data loop-back in to your application board.