I did everything as described in the wiki, but i get some errors (included the whole output though)
Could this be a driver problem? I get the same errors with the BLE sniffer.
opening configuration table from path :memory:
Config Settings
Log Level............... NOTICE
Device args............. driver=lime,device=0
TRX Base Port........... 5700
TRX Address............. 127.0.0.1
Channels................ 1
Tx Samples-per-Symbol... 4
Rx Samples-per-Symbol... 4
EDGE support............ Enabled
External Reference...... Disabled
C0 Filler Table......... Disabled
Diversity............... Disabled
Tuning offset........... 0
RSSI to dBm offset...... 0
Swap channels........... 0
-- Make connection: 'USB 3.0 (LimeSDR-USB)'
Estimated reference clock 30.7197 MHz
Selected reference clock 30.720 MHz
-- Device name: LimeSDR-USB
-- Reference: 30.72 MHz
-- Init LMS7002M(0)
LMS7002M values cache at /home/c5e3/.limesuite/LMS7002M_cache_values.db
-- Ver=7, Rev=1, Mask=1
-- LMS7002M calibration values caching Enable
CGEN: Freq=80 MHz, VCO=2.4 GHz, INT=77, FRAC=131072, DIV_OUTCH_CGEN=14
-- SoapyLMS7::setFrequency(Rx, 0, BB, 0 MHz)
-- SoapyLMS7::setFrequency(Tx, 0, BB, 0 MHz)
-- SoapyLMS7::setAntenna(Rx, 0, LNAL)
-- SoapyLMS7::setAntenna(Tx, 0, BAND1)
-- SoapyLMS7::setGain(Rx, 0, PGA, 0 dB)
-- SoapyLMS7::setGain(Rx, 0, LNA, 0 dB)
-- SoapyLMS7::setGain(Rx, 0, TIA, 0 dB)
-- SoapyLMS7::setGain(Tx, 0, PAD, -50 dB)
-- SoapyLMS7::setSampleRate(Rx, 0, 10 MHz), CGEN=80 MHz, ADC=20 MHz, decim=2
ConnectionSTREAM::ConfigureFPGA_PLL(tx=20MHz, rx=10MHz)
----- FPGA PLL #0 CONFIG -----
M=112, N=7, Fvco=640.000 MHz
C0=16, Fout=40.000 MHz, CNT_IND=2, nSteps=0, phaseShift=0.0
C1=16, Fout=40.000 MHz, CNT_IND=3, nSteps=35, phaseShift=98.4
----- FPGA PLL #1 CONFIG -----
M=93, N=3, Fvco=620.000 MHz
C0=31, Fout=20.000 MHz, CNT_IND=2, nSteps=0, phaseShift=0.0
C1=31, Fout=20.000 MHz, CNT_IND=3, nSteps=78, phaseShift=113.2
-- SoapyLMS7::setSampleRate(Tx, 0, 10 MHz), CGEN=80 MHz, DAC=20 MHz, interp=2
ConnectionSTREAM::ConfigureFPGA_PLL(tx=10MHz, rx=10MHz)
----- FPGA PLL #0 CONFIG -----
M=93, N=3, Fvco=620.000 MHz
C0=31, Fout=20.000 MHz, CNT_IND=2, nSteps=0, phaseShift=0.0
C1=31, Fout=20.000 MHz, CNT_IND=3, nSteps=65, phaseShift=94.4
----- FPGA PLL #1 CONFIG -----
M=93, N=3, Fvco=620.000 MHz
C0=31, Fout=20.000 MHz, CNT_IND=2, nSteps=0, phaseShift=0.0
C1=31, Fout=20.000 MHz, CNT_IND=3, nSteps=78, phaseShift=113.2
-- SoapyLMS7::setBandwidth(Rx, 0, 30 MHz)
-- Rx Filter calibrated from cache
-- SoapyLMS7::setBandwidth(Tx, 0, 30 MHz)
-- Tx Filter calibrated from cache
-- SoapyLMS7::setFrequency(Rx, 1, BB, 0 MHz)
-- SoapyLMS7::setFrequency(Tx, 1, BB, 0 MHz)
-- SoapyLMS7::setAntenna(Rx, 1, LNAL)
-- SoapyLMS7::setAntenna(Tx, 1, BAND1)
-- SoapyLMS7::setGain(Rx, 1, PGA, 0 dB)
-- SoapyLMS7::setGain(Rx, 1, LNA, 0 dB)
-- SoapyLMS7::setGain(Rx, 1, TIA, 0 dB)
-- SoapyLMS7::setGain(Tx, 1, PAD, -50 dB)
-- SoapyLMS7::setSampleRate(Rx, 1, 10 MHz), CGEN=80 MHz, ADC=20 MHz, decim=2
ConnectionSTREAM::ConfigureFPGA_PLL(tx=20MHz, rx=10MHz)
----- FPGA PLL #0 CONFIG -----
M=112, N=7, Fvco=640.000 MHz
C0=16, Fout=40.000 MHz, CNT_IND=2, nSteps=0, phaseShift=0.0
C1=16, Fout=40.000 MHz, CNT_IND=3, nSteps=35, phaseShift=98.4
----- FPGA PLL #1 CONFIG -----
M=93, N=3, Fvco=620.000 MHz
C0=31, Fout=20.000 MHz, CNT_IND=2, nSteps=0, phaseShift=0.0
C1=31, Fout=20.000 MHz, CNT_IND=3, nSteps=78, phaseShift=113.2
-- SoapyLMS7::setSampleRate(Tx, 1, 10 MHz), CGEN=80 MHz, DAC=20 MHz, interp=2
ConnectionSTREAM::ConfigureFPGA_PLL(tx=10MHz, rx=10MHz)
----- FPGA PLL #0 CONFIG -----
M=93, N=3, Fvco=620.000 MHz
C0=31, Fout=20.000 MHz, CNT_IND=2, nSteps=0, phaseShift=0.0
C1=31, Fout=20.000 MHz, CNT_IND=3, nSteps=65, phaseShift=94.4
----- FPGA PLL #1 CONFIG -----
M=93, N=3, Fvco=620.000 MHz
C0=31, Fout=20.000 MHz, CNT_IND=2, nSteps=0, phaseShift=0.0
C1=31, Fout=20.000 MHz, CNT_IND=3, nSteps=78, phaseShift=113.2
-- SoapyLMS7::setBandwidth(Rx, 1, 30 MHz)
-- Rx Filter calibrated from cache
-- SoapyLMS7::setBandwidth(Tx, 1, 30 MHz)
-- Tx Filter calibrated from cache
CGEN: Freq=8.66667 MHz, VCO=2.32267 GHz, INT=74, FRAC=637155, DIV_OUTCH_CGEN=133
-- SoapyLMS7::setSampleRate(Tx, 0, 1.08333 MHz), CGEN=8.66667 MHz, DAC=2.16667 MHz, interp=2
ConnectionSTREAM::ConfigureFPGA_PLL(tx=1.08333MHz, rx=1.08333MHz)
-- SoapyLMS7::setSampleRate(Tx, 1, 1.08333 MHz), CGEN=8.66667 MHz, DAC=2.16667 MHz, interp=2
ConnectionSTREAM::ConfigureFPGA_PLL(tx=1.08333MHz, rx=1.08333MHz)
-- SoapyLMS7::setSampleRate(Rx, 0, 1.08333 MHz), CGEN=8.66667 MHz, ADC=2.16667 MHz, decim=2
ConnectionSTREAM::ConfigureFPGA_PLL(tx=1.08333MHz, rx=1.08333MHz)
-- SoapyLMS7::setSampleRate(Rx, 1, 1.08333 MHz), CGEN=8.66667 MHz, ADC=2.16667 MHz, decim=2
ConnectionSTREAM::ConfigureFPGA_PLL(tx=1.08333MHz, rx=1.08333MHz)
-- SoapyLMS7::setBandwidth(Tx, 0, 5 MHz)
-- Tx Filter calibrated from cache
-- SoapyLMS7::setBandwidth(Rx, 0, 5 MHz)
-- Rx Filter calibrated from cache
-- Setting STREAM/LimeSDR EDGE mode (4 SPS TX/RX) (offset 0.086 ms = 23.2917 samples)
ERR 140134437009216 03:51:52.0 UHDDevice.cpp:871:open: TS_OFFSET = 93 rx_rate = 1.08333e+06
ERR 140134437009216 03:51:52.0 UHDDevice.cpp:871:open: TS_OFFSET = 93 rx_rate = 1.08333e+06
-- SoapyLMS7::setGain(Tx, 0, PAD, -26 dB)
-- SoapyLMS7::setGain(Rx, 0, LNA, 24.5 dB)
-- SoapyLMS7::setGain(Rx, 0, TIA, 0 dB)
-- SoapyLMS7::setGain(Rx, 0, PGA, 0 dB)
-- Transceiver active with 1 channel(s)
Warning popping from TX, samples popped 0/1360
L 174080
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Tx: 0.000 MB/s, Fs: 0.000 MHz, failures: 0, ts:0
Rx: 3.273 MB/s, Fs: 0.000 MHz, overrun: 0, loss: 0
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360
Warning popping from TX, samples popped 0/1360