I don’t think you should worry about bricking your board.
You might want to load the FX3 USB firmware using USB each time you start.
The lime is set up to boot from flash. In Linux it will appear as:
$ lsusb -s 2:3
Bus 002 Device 003: ID 1d50:6108 OpenMoko, Inc. Myriad-RF LimeSDR
If you remove the J13 jumper you will observe:
$ lsusb -s 1:7
Bus 001 Device 007: ID 04b4:00f3 Cypress Semiconductor Corp.
You’re now in the FX3 default state and can re-load the FX3 firmware:
sudo fxload -t fx3 -i LimeSDR-USB_FX3.git/Debug/LimeSDR-USB_fx3_fw.img
Note that there are different versions of fxload around so the command line above might be different for some systems. See Just trying to get started, having no luck
Then you have a new fresh FX3 firmware stored in the FX3 RAM ready for use
$ lsusb -s 2:6
Bus 002 Device 006: ID 1d50:6108 OpenMoko, Inc. Myriad-RF LimeSDR
On the FPGA side you can use a USB blaster and a conversion cable to fit the small J11 FPGA JTAG connector (described in J11 FPGA JTAG connector?). This might come handy if you have to debug the FPGA with signaltap.
You can then load the FPGA configuration into the FPGA using:
$ quartus_pgm -c 'USB-Blaster [1-3]' -m jtag -o p\;./output_files/LimeSDR-USB_lms7_trx_HW_1.4.sof
For the purpose of illustration I’ve made a FX3 and FPGA image with a different version numbers. LimeUtil will detect this:
$ LimeUtil --make
[WARNING] Firmware version mismatch!
Expected firmware version 3, but found version 4
[WARNING] Gateware version mismatch!
Expected gateware version 2, revision 9
But found version 2, revision 15
Firmware version: 4
Hardware version: 4
Protocol version: 1
Gateware version: 2
Gateware revision: 15
If you use the above method you don’t write the FX3 firmware in the on-board FLASH so a power cycle and re-connect of the J13 you will be back to normal again.
When doing FPGA design it’s common to do the bulk of the design and debugging using simulation (there’s a free/reduced version of Modelsim in the Altera distribution). However, it might be some effort to make a testbench with a FX3 model if you don’t have any experience with FPGAs. On the other hand it might be as simple as changing a queue size constant. I don’t know, I haven’t checked. It might even be that there is a queue size register which can be written for what I know. Perhaps some of the designers can give you a hint.