[LimeSDR-USB] Synchronization and Toggle TDD/FDD Mode

Projects LimeSDR
5

TDD mode for LMS7002M is activated via configuration. The idea is to use only one PLL (SXT) for both Rx and Tx chains.

Here are steps on how to do it using LimeSuiteGUI:

  1. Starting setup is as a normal FDD mode (both RX and TX synthesizers are working).
  2. Set register 0x011C[6] = 0 while 0x0020[1:0] = 2 (or SXT tab is selected in LimeSuiteGUI - uncheck control check box called “LO buffer from SXT to SXR” under “Power down controls”).
  3. Set 0x011C[1] = 1 while 0x0020[1:0] = 1 (or SXR tab is selected in LimeSuiteGUI – check control check box called “VCO” under “Power down controls”).
  4. Both receive and transmit LO frequencies are changed via TX synthesizer control (SXT) in this configuration.

Here are the steps on how to achieve the same configuration described above using Lime Suite API:
LMS_WriteParam(device, LMS7_MAC, 2);
LMS_WriteParam(device, LMS7_PD_LOCH_T2RBUF, 0);
LMS_WriteParam(device, LMS7_MAC, 1);
LMS_WriteParam(device, LMS7_PD_VCO, 1);

Here is a custom FPGA gateware:
https://github.com/myriadrf/LimeSDR-USB_GW/blob/tx_pct_sig/output_files/LimeSDR-USB_lms7_trx_HW_1.4.rbf
which activates FPGA_GPIO0 line when there are data to send. Pinout of J12 (FPGA_GPIO) is described in the Table 9 here:
https://wiki.myriadrf.org/LimeSDR-USB_hardware_description

3 Likes