I still feel Synchronize two LimeSDR can help you
I should ideally be able to capture full bandwidth without USB3 being a bottleneck
What’s the bandwidth of the signals you wish to capture?
No matter what you do, I think you’ll always be limited to around 60MS/s, whether in mono or dual channel, no matter how short and sparse your signals are. On dual channel to achieve that speed, you’ll want your samples to be encoded in complex int 12 instead of complex float 16. You won’t lose any data as the ADC works on 12 bits, you’ll just need to convert the result back to float (by dividing by 2048, as the values will be [-2048, 2048) instead of [-1, 1) ).
You could continuously receive (by blocks of 680 in dual channel or 1360 in mono channel, see Synchronize two LimeSDR for why), then you’d set the GPIO and leave it high for “long enough” (it should be at least the time needed to fill you block of samples). If it’s not long enough, you risk not been able to actually see the negative timestamp.
You could either set the GPIO a short time at the beginning and at the end of your interesting signal, or leave it on all the time then off once your interesting signal appears.
With the 2nd approach, you’d drop all block with negative timestamp, and keep those with positive timestamp. The resources needed to just receive and drop samples with negative timestamp should be pretty low. Any decent computer with a good USB3 could do that.
Also keep in mind that the timestamps are still being updated in the FPGA, so when you receive a positive timestamp, it has the same value as if you’d never set the GPIO, meaning you don’t lose any info concerning the time.