Issues with using LimeSDR in MIMO2x2 Spatial Multiplexing Mode

Dear Members,

I am making an application for angle of arrival (AoA) estimation using LimeSDR in MIMO spatial multiplexing mode. The plan is use WiFi signal for estimating the AoA.

To estimate the angle of arrival both receive antennas should be sampling at the same time and then phase difference between the received signal is used to estimate the angle. So far I have been able to setup the board in MIMO mode using both Rx antennas.

I wrote a simple application in Octave that transmits a tone of 2.5MHz from Tx1.
The carrier frequency is 2412MHz and sampling frequency is 10MHz.
I receive the signal at both Rx1 and Rx2. However, if I plot the received signal from both antennas some times there is a delay of 1 cycle.

It seems that the there is a delay of 1 sampling clock cycle between the 2 receivers. May be there is a setting in the board configuration .ini file that I need to change. Any help would be grateful ! I can also share the code on github if that will help.

Here are my questions:

  1. What is the best way to calibrate the LimeSDR? I already tried LimeSuite and LimeUtil --cal both of them dont make a lot of difference.

  2. After sometime the board heats up and the performance degrades. Is this a known issue ? How can it be solved?

  3. Has some already tried using LimeSDR in MIMO 2x2 spatial multiplexing mode?


Hello @obaidz8,

Check this resource, please:

You will find a link to calibration description in chapter “4. Documentation”.

You should use a fan if the boards heats up in your application. Check this for more details.

For data synchronization between A and B channels I would suggest this procedure:

  1. Disable clock generator, set EN_G_CGEN 0x0086[0]=0;
  2. Reset RxTSP logic registers by toggling(1->0->1) 0x0020[9] LRST_RX_A and 0x0020[11] LRST_RX_B;
  3. Enable clock generator, set EN_G_CGEN 0x0086[0]=1.
1 Like

Is there any utility for programming MCU calibration image?

I have the same problem. Check this thread. RX channels alignment

The disabling clock routine did not work for me. Also the shift seems to be random ±2samples with subsample (1/4th if remember correctly) steps. Give update if it did the job in your case.
Subsample shift may seem odd but in lms7002d we have to do with sigma delta adc operating at higher frequency than output.


Thank you very much for the help, unfortunately did not work or I am making a mistake.

I created a .ini file using LimeSuiteGUI and at the end of the file I programme the registers as:

0x0086=0x4100 #CGEN off
0x0020=0xFFF7 # toggle both bit [9] and [11]
0x0086=0x4101 # CGEN ON

The .ini file in dropbox.

  1. Is there a specific sequence of programming registers?
  2. This routine should be at the start or at the end of .ini file?

@modimo I also observe random +/- Ts difference between the samples. I think after doing this procedure the probability of +/- Ts difference decreases but it is still there.
Did you find any work around for this in software?

No i did not. I tried fiddling with registers but no luck. You can use DSP methods to fix this but it seems to be excess means. Your test case is easier to reproduce than minę, maybe lime guys will take another look at the problem.
Since limesdr allows to sync multiple boards the synchronization within single chip should be obvious. But it is not. I did put my project aside because of that. Looking forward for any update in this matter.

I can try multiple restarts until the 2Rx start synchronised.

Do you know if they REMAIN synchronised if they start synchronised? or one of the Rx drifts away?

From my experience the delay stays the same. It seems it is synchronous issue. Be careful though with restarting method. You might end up with small shift (subsample) that can easily be missed.

I created a .ini file using LimeSuiteGUI and at the end of the file I programme the registers as:

0x0086=0x4100 #CGEN off
0x0020=0xFFF7 # toggle both bit [9] and [11]
0x0086=0x4101 # CGEN ON

.ini file does not work that way, it does not produce such sequence of register writes. When .ini file contains duplicate addresses only the last value of repeating addresses is written.

@ricardas Is there a working demo of this alignment procedure?

As far as I know, no

@ricardas as mentioned by @modimo the toggling approach did not work.

can you kindly suggest any other approach that you think might work ?

currently i just keep on restarting the chip until it finds that the receivers are aligned.

Hi @obaidz8,

What firmware version are you using?
Could you share your register setup file please.

Hi zack,

I also updated the firmware using
LimeUtil --update

so I guess the latest one

The setup file on dropbox.


Hello @obaidz8,

You should do A and B channel alignment (or deciding by how many samples A and B channels are out of sync) manually each time after power up. Although there is a delay line in the LMS7002M which is able to delay up to 4 samples. Check register HBD_DLY (0x0404[15:13]) in RxTSP.

@obaidz8 Is it possible you can send me your code in Octave that can send from Tx1 and receive from Rx1 and Rx2 ? I would like to do a beamforming using LimeSDR to extend the range of communication, but because I’m new in this domain and really can’t find a lot of tutorial in octave. By now, all I have is the source code in LimeSDR workshop.
If not possible, can you suggest me some ressources for me to catch on this topic ? Thank you a lot

I’m seeing the same issue of non-synchronised Rx channels - really surprised there is no mechanism to align the data.

If an internal test signal and loopback is used to find the channel difference, would it remain constant if the loopback is switched off on-the-fly and ‘real’ signals sampled?

This does of course assume the test signal to both channels are aligned?