Generate chirp signal using Lime SDR

[Zack]

Hi @chandu,

@chandu

If that is the scenario, then i would not use interpolation and decimation.

If you want to bypass decimation/interpolation, then you still have to generate 160 MHz, just externally. The explanation is as follows:

1. You have 4 ADCs running at 80MHz in parallel; this is 4 Samples * 80 MHz = 320 MSps (mega samples per second);
2. We have one external IQ data bus. You have to transfer 320 MSps data through this single bus which translates to 320 MHz MCLK/FCLK frequency when SDR and 160 MHz MCLK/FCLK when DDR.
3. As escribed in item 1, ADCs hence TSPs as well are running @ 80MHz. And this frequency is used to construct MCLK frequency. But from item 2 we see that we need 160 MHz which is twice of ADC or TSP frequency. There is no facility to double the clock in LMS7002M hence you have to generate this frequency externally which is anyway too high for the interface.