I see in past forum posts a link to FPGA RTL project in Xilinx Vivado. The link seems to be broken. It would be greatly beneficial to have access to a reference design with the Zedboard and Zipper and Myriad.
On the GIT HUB it says placeholder. Has it even been accomplished? Or has anyone have an example project as a base?
I am looking for general constraints of FMC. The SPI VHDL code example between the FPGA and the Zipper for the VCO. Also software code for setting up LMS6002D registers.
My end target is Linux on one core of Zynq, Bare metal on other core of Zynq. Interface with LMS6002D. Initial development I would like to just be able to setup LMS6002D and TX and RX a signal.
Any suggestions on how best to interface between the Myriad ADCs and the ARM cores on the Zynq?
Currently I have tried to use generic-uio and some custom IP but I am not getting a particularly
high transfer rate. I suspect my IP is not optimal, I may however be asking too much of UIO.
I am using PetaLinux with all the GPIO/SPI/I2C routed via the FMC (an awful lot of links on
the board to change, if I ever do this again, I’ll use the PMOD connectors instead).
I work for a company up in Canada and we started our development of an RF system on the Zedboard + Zipper board + Myriad RF board. We have now moved onto our custom board using the ZYNQ SOC FPGA and the myriad board.
The zipper board is an interface board that can be used to convert from FMC to the connector of the myriad RF board.
To get the system working fully, you need to talk to the LMS6002d via spi. For Transmit you need to control the hard tx enable, the TX clock, and the 12 lines of TX DAC and TX IQ (In phase Quadrature) select. For Receive you need to give an RX Clock and the ability to receive the inputs of the 12 bits of adc and the RX IQ select. There is also a programming and calibration guide that needs to be followed. Nothing will work unless the LMS6002d is programmed properly. Our system uses petalinux on 1 core and Bare metal on the other core. We do all the SPI and calibration routines on the Bare metal.
If using the ZEDBOARD the RX adc data will come to the PL (Programmable Logic) side of the zynq. Since you are providing the RX clock you can use the RX clock to sample the RX adc data on the appropriate edge.
If you are trying to get the ADC data from the PL to the PS (Processing system aka the arm cores) there are a couple ways to do it:
Convert AXI Stream (Make a custom IP that converts ADC data into AXI Stream format) to AXI memory map using Xilinx AXI DMA ip. This video has some details although not perfect.:
Use block ram in the PL to store the amount of samples needed. Then the PS can read out the whole block ram.
This can be done using AXI bram Controller and Block memory generator AXI IP. Obviously you will need custom logic to write the RX adc data into the block ram.
Thanks for the reply. I am pretty much doing what you suggest except I am doing the SPI and I2C using the Petalinux kernel drivers. I have the TX/RX synths working and the
Si5351 generating the correct frequencies. The calibration routines are not reporting any errors.
To send / receive samples to the board I am using the UIO driver. Initially I just fudged
the code that Xilinx produces when you create a new AXI4 peripheral however that didn’t
work too well. Now with the help of
I am re-writing it to talk directly from the AXI4 interface wires to a fifo which in turn talks to
the MyriadRf HW, with a different clock domain on either side. I am using the fifo full and fifo empty flags to flow control the AXI4 side of things.
Everything just built so I will try it out later and see if it works better than my first attempt did.
I am not too familiar with the Xilinx tools, my last project was using HDL (Verilog) and
Quartus-II so there has been a big learning curve for me.
So your comments at least make me feel I am not totally barking.
Creating AXI IP and using VIVADO is huge learning curve. I have a top level block design of all the custom IP’s that i need. All my custom IP’s are done in VHDL.
Depending on what you want transmit out I use the DDS compiler Xilinx IP core to create my I Q DAC signals. I than have a custom IP that applies a window function that I store in block ram. ( Multiplies the DDS IQ output by the window function). I than apply the GAIN_I, GAIN_Q / PHASE_I, PHASE_Q Adjustments to remove the TX UNWANTED SIDE BAND (SEE the calibration guide for details)
The DDS Compiler can also be configured on the fly by the processor through an AXI interface. This will change the phase increment value (The frequency of the Sine and cosine signals).
For the Receive I sample the signals on the appropriate edge and I put it through a comb filter as suggested in the programming and calibration guide. I then remove the RX unwanted side band. I have an automatic gain control loop that will talk to the processor to adjust the Gains of the RXVGA2 RXVGA1 and LNA so the RX adcs don’t rail.
If I were you I would first try just sending a signal to the IQ dacs and see if you can receive. If you have a logic analyzer I would advise finding a way to send dac/adc data to pins on the unused PMOD connectors on the zed board. I used the 4 pmod connectors to connected to the PL to output signals to look at in the logic analyzer.
You can try different loop back modes in the LMS6002d. You might be trying to get too much working at the same time.
Note: You can use VIVADO integrated logic analyzer to view the ADC data incoming into the FPGA. It uses block rams to store data.
Thanks for the tips. My actual application will be for Digital TV transmission.
I have already designed a transmitter board that uses an ADRF6755 which operates
between 70 MHz and 2.48 Ghz. I am now looking at the next generation of the
board and I would like to include Digital Pre-distortion (DPD) which involves
comparing the output of the final PA stage with the ‘ideal signal’ and distorting
the exciter waveform to compensate for the non linearities of the amplifier chain.
Consequently the tight coupling of the receiver and transmitter channel in the
LMS6002D is important.
Ideally I would like to use a LMS7002M mainly for its lower frequency operation
but at the moment that is uneconomic. As I am just trying to produce a proof of
concept I can use the 6002.
As you say Vivado is a steep learning curve and is not helped by the fact that a
lot of Xilinx tutorials still refer to using ISE and the way that PetaLinux is built has
recently changed.
At the moment I just have a Spectrum Analyser hooked up to the transmitter so I
can see the unwanted sideband suppression etc.
My first attempt at writing my own AXI4 peripheral from scratch just locked the thing up
probably because I don’t fully understand the interface timing. I also discovered that when
you use Xilinx IP the IP packager doesn’t automatically include the Xilinx IP and the files
have to be added manually, which because I am using Verilog causes warnings as the
Xilinx stuff is VHDL.
You have run into what I call a nasty Vivado bug! You can do AXI peripheral in both Verilog and VHDL. Xilinx has templates for both languages. Their is a bug with the vivado tool that sometimes creates the wrong HDL template. Make sure you have selected the correct language in project settings. Retry 3-5 times, I couldn’t figure out exactly how to get it into the language of my choice but eventually it works.
It appears to be full of bugs. However I think my problem was slightly different in that I was
generating RTL using the fifo builder tool, it appears to generate VHDL with a Verilog
wrapper. It was when I came to use the IP packager that things didn’t work as expected
and I manually had to add the .xci file to the package.
I’m looking for a dev. board with a simple “ZYNQ SOC FPGA and myriadRF board” to learn SDR, in particular experimenting with GSM and RF measurement… etc.
Are you “selling” your custom board? (I’m in Canada too, precisely in Quebec!)
The zipper board is basically an interface board that connects the myriad to a zedboard (FMC connector) or altera dev board (HSMC).
Of course you need a myriad RF.
These three boards should give you all the tools to start experimenting. It is a lot of work to get it up in running between learning ZYNQ, and LMS6002d programming and calibration guide.
I worked with the development boards above for about 6 months. I have been working with my custom boards for our specific application for about 6 months now.
Note: There are a few things to iron out with the zipper board. For example removing resistors and soldering resistors in other areas on the board.
If you have any other questions I am glad to help.
Vitia,
another solution is using the SOM(system on module) from NI with zipper and myriad RF. The advantage of SOM is using LABVIEW for pragramming FPGA. That’s a graphical programming language, so you don’t need much knowledge about FPGAs.
That is the kind of optimal solution (NI sbRIO-9651 SoM) for me. The only issue is the availability of the product for hobbyist. NI offers only OEM quantity.
Zedboard: I don’t need most of the Zedboard components actually but it seems to be the only practical solution so far…
Interface to Parallella would not bad too. I will be able to build a zipper board but not something like Parallella-RF.
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