XTRX and Amarisoft (reference configuration file)

I’m trying to use XTRX together with Amarisoft (UE, eNB and gNB). After some tweaking, I managed to get XTRX to work using the new LimeSuiteNG plugin. However, I’m having problems with synchronization. I think it must be some fine tuning. Does anyone have a reference file for XTRX to work with Amarisoft? My radio settings are currently:

rf_driver: {
    name: "limesuite",
    logLevel: 5, 
    dev0: "LimeXTRX0",
    port0: "dev0",
    
    
    port0_rx_path: "LNAH",
    port0_tx_path: "BAND2",
    dev0_rx_calibration: "all", 
    dev0_tx_calibration: "all",

    },
    tx_time_offset: -72, 
    tx_pad_duration: 30, 
    rx_ta_offset: 22
    tx_gain: 66.0, 
    rx_gain: 47.0,

Some of these values are based on the settings I used with srsRAN 4G and which worked. Talking about that: are there any plans for integration with the srsRAN Project (5G)?

1 Like

Tagging @karolis.

Yes and while there is no definite timeline, but I’d expect to have this at some point within the next few months

Hello,

this could be used as reference.

Amarisoft configuration:
/*
Port has a dev list that will be used by Amarisoft to construct its cell
Dev can be MIMO or SIMO depending on devX_max_channels_to_use value (1 = 1, none or 2 = 2)
If devX_ini value is specffied, this deviced will be loaded with the appropriate .ini file even if not used in port list. Can be used to switch off dev
Dev should be incremental, but chip index does not. Dev is like logical hardware, while chip is the “true” sdr selection. Port is the list of devs that implement cell required RF paths.
"port > dev > "
*/

//tx_time_offset: -100, /* normally slightly negative*/
//tx_pad_duration: 30, //40
//rx_ta_offset: 22, //24, 26 max
tx_gain: 50, // TX gain (in dB). If array, defines each channel gain (0,1,2 …)
rx_gain: 17.0, // RX gain (in dB). If array, defines each channel gain (0,1,2 …)

rf_driver: {
name: “limesuite”,
logLevel: 3, // OPTIONAL, enable printing of additional information: 0-critical, (default)1-error, 2-warning, 3-info, 4-verbose, 5-debug

//---------------------------------------- Port aggregate ----------------------------------------//

port0: "dev0",

//---------------------------------------- Port defaults ----------------------------------------//

port0_ini: "lms_xtrx_mimo_26p00.ini", // OPTIONAL, will use defaults settings as base
port0_max_channels_to_use: 2,	
port0_rx_path: "LNAH",
port0_tx_path: "BAND1",
//port0_rx_lo_override: 1.9e6, // OPTIONAL, force set RxLO frequency
//port0_tx_lo_override: 2.0e6, // OPTIONAL, force set TxLO frequency
port0_rx_oversample: 0, // OPTIONAL, by default 0 (automatic max available oversample), 1, 2, 4, 8...
port0_tx_oversample: 0, // OPTIONAL, by default 0 (automatic max available oversample), 1, 2, 4, 8...
port0_rx_gfir_enable: 0, // OPTIONAL, by default 0
//port0_rx_gfir_bandwidth: 5e6, // OPTIONAL, by default is set to host's expected bandwidth
port0_tx_gfir_enable: 0, // OPTIONAL, by default 0
//port0_tx_gfir_bandwidth: 5e6, // OPTIONAL, by default is set to host's expected bandwidth
port0_lpf_bandwidth_scale: 1.0, // OPTIONAL, multiplier for requested LPF bandwidth, default 1.0
port0_rx_power_dBm: 0+14, // OPTIONAL, hint about absolute RX power in dBm, assuming a square signal of maximum amplitude
port0_tx_power_dBm: 0+14, // OPTIONAL, hint about absolute TX power in dBm, assuming a square signal of maximum amplitude
port0_rx_calibration: "none", /*all, none, filter, dciq */
port0_tx_calibration: "none", /*all, none, filter, dciq */
//port0_linkFormat: "I16" // OPTIONAL, data format for transfering: I12, I16
//port0_syncPPS: 1, // OPTIONAL, start sampling on next PPS, default 0
//port0_double_freq_conversion_to_lower_side: 1 // OPTIONAL, negates Q channel value   

//---------------------------------------- Device override ----------------------------------------//

dev0: "XTRX",
dev0_chip_index: 0, // OPTIONAL, will use 0 if not specified
//dev0_ini: "OFF.ini", // OPTIONAL, will use defaults settings as base

//---------------------------------------- TBD ----------------------------------------//

//dev0_writeRegisters: "AAAABBBB;CCCCDDDD"; // OPTIONAL, 32bit(16:addr, 16:data) SPI values to be written to FPGA

// XTRX controls
//a[11] - LimeXTRX RF switch auto TDD swithcing. 0 - disabled; 1 - enabled. Active value based on a[4:2]. On DL side selected TX path active, RX terminated and vice versa 
//a[4] 0 - TX band 2; 1 - TX band 1
//a[3:2] 0 - RX W; 1 - RX L; 2 - RX H; 3 - None, terminated
//10[15:0] and 11[15:0] - start and stop delay for TDD signal
// EXAMPLES: dev0_writeRegisters: "a0818;1000b0;1100b0" - TDD; dev0_writeRegisters: "a0004;100000;110000" - FDD TX2 RXL

},

Karolis

Thank you very much for the answers,

@Karolis , could you kindly share this lms_xtrx_mimo_26p00.ini file (or point me where to find it)?

Regards,

.ini file is not required, it’s only for the purpose of fine adjusting of chip parameters that are not generic to an SDR.

Hello,

I cannot attach the .ini file directly due to file format resitrictions, but I will paste the contents of the .ini file and you can make one. As @ricardas mentioned, this file is not mandatory.

[file_info]
type=lms7002m_minimal_config
version=1
[lms7002_registers_a]
0x0020=0xFFFD
//LRST_TX_B : 1
//MRST_TX_B : 1
//LRST_TX_A : 1
//MRST_TX_A : 1
//LRST_RX_B : 1
//MRST_RX_B : 1
//LRST_RX_A : 1
//MRST_RX_A : 1
//SRST_RXFIFO : 1
//SRST_TXFIFO : 1
//RXEN_B : 1
//RXEN_A : 1
//TXEN_B : 1
//TXEN_A : 1
//MAC : 1
0x0021=0x0E9F
//TX_CLK_PE : 1
//RX_CLK_PE : 1
//SDA_PE : 1
//SDA_DS : 0
//SCL_PE : 1
//SCL_DS : 0
//SDIO_DS : 0
//SDIO_PE : 1
//SDO_PE : 1
//SCLK_PE : 1
//SEN_PE : 1
//SPIMODE : 1
0x0022=0x07DF
//DIQ2_DS : 0
//DIQ2_PE : 1
//IQ_SEL_EN_2_PE : 1
//TXNRX2_PE : 1
//FCLK2_PE : 1
//MCLK2_PE : 1
//DIQ1_DS : 0
//DIQ1_PE : 1
//IQ_SEL_EN_1_PE : 1
//TXNRX1_PE : 1
//FCLK1_PE : 1
//MCLK1_PE : 1
//LML2_TRXIQPULSE : 0
//LML2_SISODDR : 0
//LML1_TRXIQPULSE : 0
//LML1_SISODDR : 0
0x0023=0x5550
//DIQDIRCTR2 : 0
//DIQDIR2 : 1
//DIQDIRCTR1 : 0
//DIQDIR1 : 1
//ENABLEDIRCTR2 : 0
//ENABLEDIR2 : 1
//ENABLEDIRCTR1 : 0
//ENABLEDIR1 : 1
//MOD_EN : 1
//LML2_FIDM : 0
//LML2_TXNRXIQ : 1
//LML2_MODE : 0
//LML1_FIDM : 0
//LML1_TXNRXIQ : 0
//LML1_MODE : 0
0x0024=0xE4E4
//LML1_S3S : 3
//LML1_S2S : 2
//LML1_S1S : 1
//LML1_S0S : 0
//LML1_BQP : 3
//LML1_BIP : 2
//LML1_AQP : 1
//LML1_AIP : 0
0x0025=0x0101
//LML1_BB2RF_PST : 1
//LML1_BB2RF_PRE : 1
0x0026=0x0101
//LML1_RF2BB_PST : 1
//LML1_RF2BB_PRE : 1
0x0027=0xE4E4
//LML2_S3S : 3
//LML2_S2S : 2
//LML2_S1S : 1
//LML2_S0S : 0
//LML2_BQP : 3
//LML2_BIP : 2
//LML2_AQP : 1
//LML2_AIP : 0
0x0028=0x0101
//LML2_BB2RF_PST : 1
//LML2_BB2RF_PRE : 1
0x0029=0x0101
//LML2_RF2BB_PST : 1
//LML2_RF2BB_PRE : 1
0x002A=0x0086
//FCLK2_DLY : 0
//FCLK1_DLY : 0
//RX_MUX : 0
//TX_MUX : 0
//TXRDCLK_MUX : 2
//TXWRCLK_MUX : 0
//RXRDCLK_MUX : 1
//RXWRCLK_MUX : 2
0x002B=0x0038
//FCLK2_INV : 0
//FCLK1_INV : 0
//MCLK2DLY : 0
//MCLK1DLY : 0
//MCLK2SRC : 3
//MCLK1SRC : 2
//TXDIVEN : 0
//RXDIVEN : 0
//MCLK2_DLY : 0
//MCLK1_DLY : 0
//MCLK2_INV : 0
//MCLK1_INV : 0
0x002C=0x0000
//TXTSPCLKA_DIV : 0
//RXTSPCLKA_DIV : 0
0x002D=0x0641
0x002E=0x0000
//MIMO_SISO : 0
0x002F=0x3841
//VER : 7
//REV : 1
//MASK : 1
0x0081=0x0001
//EN_DIR_LDO : 0
//EN_DIR_CGEN : 0
//EN_DIR_XBUF : 0
//EN_DIR_AFE : 1
//TRX_GAIN_SRC : 0
0x0082=0x8001
//ISEL_DAC_AFE : 4
//MODE_INTERLEAVE_AFE : 0
//MUX_AFE_1 : 0
//MUX_AFE_2 : 0
//PD_AFE : 0
//PD_RX_AFE1 : 0
//PD_RX_AFE2 : 0
//PD_TX_AFE1 : 0
//PD_TX_AFE2 : 0
//EN_G_AFE : 1
0x0084=0x0400
//MUX_BIAS_OUT : 0
//RP_CALIB_BIAS : 16
//PD_FRP_BIAS : 0
//PD_F_BIAS : 0
//PD_PTRP_BIAS : 0
//PD_PT_BIAS : 0
//PD_BIAS_MASTER : 0
0x0085=0x0001
//SLFB_XBUF_RX : 0
//SLFB_XBUF_TX : 0
//BYP_XBUF_RX : 0
//BYP_XBUF_TX : 0
//EN_OUT2_XBUF_TX : 0
//EN_TBUFIN_XBUF_RX : 0
//PD_XBUF_RX : 0
//PD_XBUF_TX : 0
//EN_G_XBUF : 1
0x0086=0x4101
//SPDUP_VCO_CGEN : 0
//RESET_N_CGEN : 1
//EN_ADCCLKH_CLKGN : 0
//EN_COARSE_CKLGEN : 0
//EN_INTONLY_SDM_CGEN : 0
//EN_SDM_CLK_CGEN : 1
//PD_CP_CGEN : 0
//PD_FDIV_FB_CGEN : 0
//PD_FDIV_O_CGEN : 0
//PD_SDM_CGEN : 0
//PD_VCO_CGEN : 0
//PD_VCO_COMP_CGEN : 0
//EN_G_CGEN : 1
0x0087=0x21DE
//FRAC_SDM_CGEN_LSB : 8670
0x0088=0x0541
//INT_SDM_CGEN : 84
//FRAC_SDM_CGEN_MSB : 1
0x0089=0x1040
//REV_SDMCLK_CGEN : 0
//SEL_SDMCLK_CGEN : 0
//SX_DITHER_EN_CGEN : 0
//CLKH_OV_CLKL_CGEN : 2
//DIV_OUTCH_CGEN : 8
//TST_CGEN : 0
0x008A=0x0514
//REV_CLKDAC_CGEN : 0
//REV_CLKADC_CGEN : 0
//REVPH_PFD_CGEN : 0
//IOFFSET_CP_CGEN : 20
//IPULSE_CP_CGEN : 20
0x008B=0x21A4
//CMPLO_CTRL_CGEN : 0
//ICT_VCO_CGEN : 16
//CSW_VCO_CGEN : 210
//COARSE_START_CGEN : 0
//CMPLO_CTRL_CGEN : 0
0x008C=0x267B
//COARSE_STEPDONE_CGEN : 0
//COARSEPLL_COMPO_CGEN : 0
//VCO_CMPHO_CGEN : 1
//VCO_CMPLO_CGEN : 0
//CP2_CGEN : 6
//CP3_CGEN : 7
//CZ_CGEN : 11
0x0092=0x0001
//EN_LDO_DIG : 0
//EN_LDO_DIGGN : 0
//EN_LDO_DIGSXR : 0
//EN_LDO_DIGSXT : 0
//EN_LDO_DIVGN : 0
//EN_LDO_DIVSXR : 0
//EN_LDO_DIVSXT : 0
//EN_LDO_LNA12 : 0
//EN_LDO_LNA14 : 0
//EN_LDO_MXRFE : 0
//EN_LDO_RBB : 0
//EN_LDO_RXBUF : 0
//EN_LDO_TBB : 0
//EN_LDO_TIA12 : 0
//EN_LDO_TIA14 : 0
//EN_G_LDO : 1
0x0093=0x0000
//EN_LOADIMP_LDO_TLOB : 0
//EN_LOADIMP_LDO_TPAD : 0
//EN_LOADIMP_LDO_TXBUF : 0
//EN_LOADIMP_LDO_VCOGN : 0
//EN_LOADIMP_LDO_VCOSXR : 0
//EN_LOADIMP_LDO_VCOSXT : 0
//EN_LDO_AFE : 0
//EN_LDO_CPGN : 0
//EN_LDO_CPSXR : 0
//EN_LDO_TLOB : 0
//EN_LDO_TPAD : 0
//EN_LDO_TXBUF : 0
//EN_LDO_VCOGN : 0
//EN_LDO_VCOSXR : 0
//EN_LDO_VCOSXT : 0
//EN_LDO_CPSXT : 0
0x0094=0x0000
//EN_LOADIMP_LDO_CPSXT : 0
//EN_LOADIMP_LDO_DIG : 0
//EN_LOADIMP_LDO_DIGGN : 0
//EN_LOADIMP_LDO_DIGSXR : 0
//EN_LOADIMP_LDO_DIGSXT : 0
//EN_LOADIMP_LDO_DIVGN : 0
//EN_LOADIMP_LDO_DIVSXR : 0
//EN_LOADIMP_LDO_DIVSXT : 0
//EN_LOADIMP_LDO_LNA12 : 0
//EN_LOADIMP_LDO_LNA14 : 0
//EN_LOADIMP_LDO_MXRFE : 0
//EN_LOADIMP_LDO_RBB : 0
//EN_LOADIMP_LDO_RXBUF : 0
//EN_LOADIMP_LDO_TBB : 0
//EN_LOADIMP_LDO_TIA12 : 0
//EN_LOADIMP_LDO_TIA14 : 0
0x0095=0x0000
//BYP_LDO_TBB : 0
//BYP_LDO_TIA12 : 0
//BYP_LDO_TIA14 : 0
//BYP_LDO_TLOB : 0
//BYP_LDO_TPAD : 0
//BYP_LDO_TXBUF : 0
//BYP_LDO_VCOGN : 0
//BYP_LDO_VCOSXR : 0
//BYP_LDO_VCOSXT : 0
//EN_LOADIMP_LDO_AFE : 0
//EN_LOADIMP_LDO_CPGN : 0
//EN_LOADIMP_LDO_CPSXR : 0
0x0096=0x0000
//BYP_LDO_AFE : 0
//BYP_LDO_CPGN : 0
//BYP_LDO_CPSXR : 0
//BYP_LDO_CPSXT : 0
//BYP_LDO_DIG : 0
//BYP_LDO_DIGGN : 0
//BYP_LDO_DIGSXR : 0
//BYP_LDO_DIGSXT : 0
//BYP_LDO_DIVGN : 0
//BYP_LDO_DIVSXR : 0
//BYP_LDO_DIVSXT : 0
//BYP_LDO_LNA12 : 0
//BYP_LDO_LNA14 : 0
//BYP_LDO_MXRFE : 0
//BYP_LDO_RBB : 0
//BYP_LDO_RXBUF : 0
0x0097=0x0000
//SPDUP_LDO_DIVSXR : 0
//SPDUP_LDO_DIVSXT : 0
//SPDUP_LDO_LNA12 : 0
//SPDUP_LDO_LNA14 : 0
//SPDUP_LDO_MXRFE : 0
//SPDUP_LDO_RBB : 0
//SPDUP_LDO_RXBUF : 0
//SPDUP_LDO_TBB : 0
//SPDUP_LDO_TIA12 : 0
//SPDUP_LDO_TIA14 : 0
//SPDUP_LDO_TLOB : 0
//SPDUP_LDO_TPAD : 0
//SPDUP_LDO_TXBUF : 0
//SPDUP_LDO_VCOGN : 0
//SPDUP_LDO_VCOSXR : 0
//SPDUP_LDO_VCOSXT : 0
0x0098=0x0000
//SPDUP_LDO_AFE : 0
//SPDUP_LDO_CPGN : 0
//SPDUP_LDO_CPSXR : 0
//SPDUP_LDO_CPSXT : 0
//SPDUP_LDO_DIG : 0
//SPDUP_LDO_DIGGN : 0
//SPDUP_LDO_DIGSXR : 0
//SPDUP_LDO_DIGSXT : 0
//SPDUP_LDO_DIVGN : 0
0x0099=0x6565
//RDIV_VCOSXR : 101
//RDIV_VCOSXT : 101
0x009A=0x658C
//RDIV_TXBUF : 101
//RDIV_VCOGN : 140
0x009B=0x8C65
//RDIV_TLOB : 140
//RDIV_TPAD : 101
0x009C=0x658C
//RDIV_TIA12 : 101
//RDIV_TIA14 : 140
0x009D=0x6565
//RDIV_RXBUF : 101
//RDIV_TBB : 101
0x009E=0x8C65
//RDIV_MXRFE : 140
//RDIV_RBB : 101
0x009F=0x658C
//RDIV_LNA12 : 101
//RDIV_LNA14 : 140
0x00A0=0x658C
//RDIV_DIVSXR : 101
//RDIV_DIVSXT : 140
0x00A1=0x6565
//RDIV_DIGSXT : 101
//RDIV_DIVGN : 101
0x00A2=0x6565
//RDIV_DIGGN : 101
//RDIV_DIGSXR : 101
0x00A3=0x6565
//RDIV_CPSXT : 101
//RDIV_DIG : 101
0x00A4=0x6565
//RDIV_CPGN : 101
//RDIV_CPSXR : 101
0x00A5=0x6565
//RDIV_SPIBUF : 101
//RDIV_AFE : 101
0x00A6=0x000F
//SPDUP_LDO_SPIBUF : 0
//SPDUP_LDO_DIGIp2 : 0
//SPDUP_LDO_DIGIp1 : 0
//BYP_LDO_SPIBUF : 0
//BYP_LDO_DIGIp2 : 0
//BYP_LDO_DIGIp1 : 0
//EN_LOADIMP_LDO_SPIBUF : 0
//EN_LOADIMP_LDO_DIGIp2 : 0
//EN_LOADIMP_LDO_DIGIp1 : 0
//PD_LDO_SPIBUF : 1
//PD_LDO_DIGIp2 : 1
//PD_LDO_DIGIp1 : 1
//EN_G_LDOP : 1
//ISINK_SPI_BUFF : 0
0x00A7=0x6565
//RDIV_DIGIp2 : 101
//RDIV_DIGIp1 : 101
0x00A8=0x0000
//BSIGT : 0
//BSTATE : 0
//EN_SDM_TSTO_SXT : 0
//EN_SDM_TSTO_SXR : 0
//EN_SDM_TSTO_CGEN : 0
//BENC : 0
//BENR : 0
//BENT : 0
//BSTART : 0
0x00A9=0x8000
0x00AA=0x0000
//BSIGR : 0
0x00AB=0x0040
//BSIGC : 0
0x00AC=0x2000
0x00AD=0x03FF
//CDS_MCLK2 : 0
//CDS_MCLK1 : 0
//CDSN_TXBTSP : 1
//CDSN_TXATSP : 1
//CDSN_RXBTSP : 1
//CDSN_RXATSP : 1
//CDSN_TXBLML : 1
//CDSN_TXALML : 1
//CDSN_RXBLML : 1
//CDSN_RXALML : 1
//CDSN_MCLK2 : 1
//CDSN_MCLK1 : 1
0x00AE=0x0000
//CDS_TXBTSP : 0
//CDS_TXATSP : 0
//CDS_RXBTSP : 0
//CDS_RXATSP : 0
//CDS_TXBLML : 0
//CDS_TXALML : 0
//CDS_RXBLML : 0
//CDS_RXALML : 0
0x0100=0x7409
//EN_LOWBWLOMX_TMX_TRF : 0
//EN_NEXTTX_TRF : 1
//EN_AMPHF_PDET_TRF : 3
//LOADR_PDET_TRF : 1
//PD_PDET_TRF : 1
//PD_TLOBUF_TRF : 0
//PD_TXPAD_TRF : 0
//EN_G_TRF : 1
0x0101=0x1800
//F_TXPAD_TRF : 0
//L_LOOPB_TXPAD_TRF : 3
//LOSS_LIN_TXPAD_TRF : 0
//LOSS_MAIN_TXPAD_TRF : 0
//EN_LOOPB_TXPAD_TRF : 0
0x0102=0x3180
//GCAS_GNDREF_TXPAD_TRF : 0
//ICT_LIN_TXPAD_TRF : 12
//ICT_MAIN_TXPAD_TRF : 12
//VGCAS_TXPAD_TRF : 0
0x0103=0x0A50
//SEL_BAND1_TRF : 1
//SEL_BAND2_TRF : 0
//LOBIASN_TXM_TRF : 18
//LOBIASP_TXX_TRF : 16
0x0104=0x0088
//CDC_I_TRF : 8
//CDC_Q_TRF : 8
0x0105=0x0011
//STATPULSE_TBB : 0
//LOOPB_TBB : 0
//PD_LPFH_TBB : 1
//PD_LPFIAMP_TBB : 0
//PD_LPFLAD_TBB : 0
//PD_LPFS5_TBB : 0
//EN_G_TBB : 1
0x0106=0x318C
//ICT_LPFS5_F_TBB : 12
//ICT_LPFS5_PT_TBB : 12
//ICT_LPF_H_PT_TBB : 12
0x0107=0x318C
//ICT_LPFH_F_TBB : 12
//ICT_LPFLAD_F_TBB : 12
//ICT_LPFLAD_PT_TBB : 12
0x0108=0x410C
//CG_IAMP_TBB : 16
//ICT_IAMP_FRP_TBB : 8
//ICT_IAMP_GG_FRP_TBB : 12
0x0109=0x20C0
//RCAL_LPFH_TBB : 32
//RCAL_LPFLAD_TBB : 192
0x010A=0x1FFF
//TSTIN_TBB : 0
//BYPLADDER_TBB : 0
//CCAL_LPFLAD_TBB : 31
//RCAL_LPFS5_TBB : 255
0x010B=0x0001
//R5_LPF_BYP_TBB : 1
0x010C=0x8865
//CDC_I_RFE : 8
//CDC_Q_RFE : 8
//PD_LNA_RFE : 0
//PD_RLOOPB_1_RFE : 1
//PD_RLOOPB_2_RFE : 1
//PD_MXLOBUF_RFE : 0
//PD_QGEN_RFE : 0
//PD_RSSI_RFE : 1
//PD_TIA_RFE : 0
//EN_G_RFE : 1
0x010D=0x009F
//SEL_PATH_RFE : 1
//EN_DCOFF_RXFE_RFE : 0
//EN_INSHSW_LB1_RFE : 1
//EN_INSHSW_LB2_RFE : 1
//EN_INSHSW_L_RFE : 1
//EN_INSHSW_W_RFE : 1
//EN_NEXTRX_RFE : 1
0x010E=0x0000
//DCOFFI_RFE : 0
//DCOFFQ_RFE : 0
0x010F=0x3042
//ICT_LOOPB_RFE : 12
//ICT_TIAMAIN_RFE : 2
//ICT_TIAOUT_RFE : 2
0x0110=0x2B14
//ICT_LNACMO_RFE : 10
//ICT_LNA_RFE : 24
//ICT_LODC_RFE : 20
0x0111=0x0000
//CAP_RXMXO_RFE : 0
//CGSIN_LNA_RFE : 0
0x0112=0x2106
//CCOMP_TIA_RFE : 2
//CFB_TIA_RFE : 262
0x0113=0x01C1
//G_LNA_RFE : 7
//G_RXLOOPB_RFE : 0
//G_TIA_RFE : 1
0x0114=0x01B0
//RCOMP_TIA_RFE : 13
//RFB_TIA_RFE : 16
0x0115=0x0009
//EN_LB_LPFH_RBB : 0
//EN_LB_LPFL_RBB : 0
//PD_LPFH_RBB : 1
//PD_LPFL_RBB : 0
//PD_PGA_RBB : 0
//EN_G_RBB : 1
0x0116=0x8180
//R_CTL_LPF_RBB : 16
//RCC_CTL_LPFH_RBB : 1
//C_CTL_LPFH_RBB : 128
0x0117=0x2044
//RCC_CTL_LPFL_RBB : 4
//C_CTL_LPFL_RBB : 68
0x0118=0x018C
//INPUT_CTL_PGA_RBB : 0
//ICT_LPF_IN_RBB : 12
//ICT_LPF_OUT_RBB : 12
0x0119=0x528C
//OSW_PGA_RBB : 0
//ICT_PGA_OUT_RBB : 20
//ICT_PGA_IN_RBB : 20
//G_PGA_RBB : 12
0x011A=0x3001
//RCC_CTL_PGA_RBB : 24
//C_CTL_PGA_RBB : 1
0x011C=0x8141
//RESET_N : 1
//SPDUP_VCO : 0
//BYPLDO_VCO : 0
//EN_COARSEPLL : 0
//CURLIM_VCO : 0
//EN_DIV2_DIVPROG : 0
//EN_INTONLY_SDM : 0
//EN_SDM_CLK : 1
//PD_FBDIV : 0
//PD_LOCH_T2RBUF : 1
//PD_CP : 0
//PD_FDIV : 0
//PD_SDM : 0
//PD_VCO_COMP : 0
//PD_VCO : 0
//EN_G : 1
0x011D=0xD89D
//FRAC_SDM_LSB : 55453
0x011E=0x0BE9
//INT_SDM : 190
//FRAC_SDM_MSB : 9
0x011F=0x3602
//PW_DIV2_LOCH : 3
//PW_DIV4_LOCH : 3
//DIV_LOCH : 0
//TST_SX : 0
//SEL_SDMCLK : 0
//SX_DITHER_EN : 1
//REV_SDMCLK : 0
0x0120=0xC5FF
//VDIV_VCO : 197
//ICT_VCO : 255
0x0121=0x37F8
//RSEL_LDO_VCO : 6
//CSW_VCO : 255
//SEL_VCO : 0
//COARSE_START : 0
0x0122=0x0654
//REVPH_PFD : 0
//IOFFSET_CP : 25
//IPULSE_CP : 20
//RZ_CTRL : 0
//CMPLO_CTRL_SX : 0
0x0123=0x067B
//COARSE_STEPDONE : 0
//COARSEPLL_COMPO : 0
//VCO_CMPHO : 0
//VCO_CMPLO : 0
//CP2_PLL : 6
//CP3_PLL : 7
//CZ : 11
0x0124=0x001F
//EN_DIR_SXRSXT : 1
//EN_DIR_RBB : 1
//EN_DIR_RFE : 1
//EN_DIR_TBB : 1
//EN_DIR_TRF : 1
0x0125=0x9400
//CG_IAMP_TBB_R3 : 37
//LOSS_LIN_TXPAD_R3 : 0
//LOSS_MAIN_TXPAD_R3 : 0
0x0126=0x12FF
//C_CTL_PGA_RBB_R3 : 2
//G_PGA_RBB_R3 : 11
//G_LNA_RFE_R3 : 15
//G_TIA_RFE_R3 : 3
0x0200=0x0081
//TSGFC_TXTSP : 0
//TSGFCW_TXTSP : 1
//TSGDCLDQ_TXTSP : 0
//TSGDCLDI_TXTSP : 0
//TSGSWAPIQ_TXTSP : 0
//TSGMODE_TXTSP : 0
//INSEL_TXTSP : 0
//BSTART_TXTSP : 0
//EN_TXTSP : 1
0x0201=0x07FF
//GCORRQ_TXTSP : 2047
0x0202=0x07FF
//GCORRI_TXTSP : 2047
0x0203=0x0000
//HBI_OVR_TXTSP : 0
//IQCORR_TXTSP : 0
0x0204=0x0000
//DCCORRI_TXTSP : 0
//DCCORRQ_TXTSP : 0
0x0205=0x070F
//GFIR1_L_TXTSP : 7
//GFIR1_N_TXTSP : 15
0x0206=0x070F
//GFIR2_L_TXTSP : 7
//GFIR2_N_TXTSP : 15
0x0207=0x070F
//GFIR3_L_TXTSP : 7
//GFIR3_N_TXTSP : 15
0x0208=0x0178
//CMIX_GAIN_TXTSP : 0
//CMIX_SC_TXTSP : 0
//CMIX_BYP_TXTSP : 1
//ISINC_BYP_TXTSP : 0
//GFIR3_BYP_TXTSP : 1
//GFIR2_BYP_TXTSP : 1
//GFIR1_BYP_TXTSP : 1
//DC_BYP_TXTSP : 1
//GC_BYP_TXTSP : 0
//PH_BYP_TXTSP : 0
//CMIX_GAIN_TXTSP_R3 : 0
0x0209=0x0000
//BSIGI_TXTSP : 0
//BSTATE_TXTSP : 0
0x020A=0x0080
//BSIGQ_TXTSP : 0
0x020B=0x4000
0x020C=0x3FFF
//DC_REG_TXTSP : 16383
0x0240=0x0020
//DTHBIT_TX : 1
//SEL_TX : 0
//MODE_TX : 0
0x0241=0x0000
0x0242=0x0085
0x0243=0x5555
0x0244=0x029A
0x0245=0xAAAA
0x0246=0x0535
0x0247=0x5555
0x0248=0x07D0
0x0249=0x0000
0x024A=0x0A6A
0x024B=0xAAAA
0x024C=0x0D05
0x024D=0x5555
0x024E=0x0000
0x024F=0x0000
0x0250=0x0000
0x0251=0x0000
0x0252=0x0000
0x0253=0x0000
0x0254=0x0000
0x0255=0x0000
0x0256=0x0000
0x0257=0x0000
0x0258=0x0000
0x0259=0x0000
0x025A=0x0000
0x025B=0x0000
0x025C=0x0000
0x025D=0x0000
0x025E=0x0000
0x025F=0x0000
0x0260=0x0000
0x0261=0x0000
0x0280=0x4672
0x0281=0xFF17
0x0282=0x9857
0x0283=0x14AF
0x0284=0x0ECB
0x0285=0x2E28
0x0286=0xFDC9
0x0287=0xF784
0x0288=0x6683
0x0289=0x70E9
0x028A=0x8012
0x028B=0xE5CE
0x028C=0x59FC
0x028D=0x1EBC
0x028E=0x93E0
0x028F=0xE351
0x0290=0x421F
0x0291=0x61AC
0x0292=0xFBAA
0x0293=0xC62C
0x0294=0xAACA
0x0295=0x3018
0x0296=0xF4AE
0x0297=0xA8B9
0x0298=0x028D
0x0299=0x401A
0x029A=0x0842
0x029B=0xFC5A
0x029C=0xA6A0
0x029D=0x0D35
0x029E=0x8D29
0x029F=0x41D9
0x02A0=0xC08F
0x02A1=0xFDC9
0x02A2=0x8AC1
0x02A3=0x0211
0x02A4=0x066E
0x02A5=0x2C87
0x02A6=0xB894
0x02A7=0x2301
0x02C0=0xCADE
0x02C1=0x3E8E
0x02C2=0x2298
0x02C3=0xFBC4
0x02C4=0xC017
0x02C5=0x8D73
0x02C6=0xA65A
0x02C7=0x3CF2
0x02C8=0xE808
0x02C9=0x6278
0x02CA=0xC25E
0x02CB=0x0521
0x02CC=0x3BCC
0x02CD=0x4234
0x02CE=0xFCF3
0x02CF=0xFBE7
0x02D0=0x0B49
0x02D1=0x1877
0x02D2=0x1D33
0x02D3=0xC018
0x02D4=0x5DF2
0x02D5=0xFBAA
0x02D6=0x90CD
0x02D7=0x2941
0x02D8=0xFBE7
0x02D9=0xC1F0
0x02DA=0x05BD
0x02DB=0x9483
0x02DC=0x1929
0x02DD=0x8865
0x02DE=0xB729
0x02DF=0xD088
0x02E0=0xF043
0x02E1=0x0425
0x02E2=0x40C4
0x02E3=0x50E8
0x02E4=0xFECD
0x02E5=0xAAAD
0x02E6=0x8827
0x02E7=0x4442
0x0300=0x0000
0x0301=0xB228
0x0302=0x7A13
0x0303=0x71DD
0x0304=0x0006
0x0305=0x0A16
0x0306=0x4C13
0x0307=0x000A
0x0308=0x4DA8
0x0309=0xB9B6
0x030A=0xC492
0x030B=0x05BC
0x030C=0x000C
0x030D=0x05B5
0x030E=0x38B9
0x030F=0x3138
0x0310=0x7C3D
0x0311=0x1018
0x0312=0x0CE7
0x0313=0x4AD8
0x0314=0x58AF
0x0315=0xB7F7
0x0316=0xE8E9
0x0317=0x45E9
0x0318=0x00E7
0x0319=0x3A20
0x031A=0xE9C0
0x031B=0x0CA2
0x031C=0x2735
0x031D=0x4144
0x031E=0x0094
0x031F=0xFF5F
0x0320=0xA006
0x0321=0xB540
0x0322=0x0908
0x0323=0x4042
0x0324=0x00A6
0x0325=0x0E7B
0x0326=0x00AE
0x0327=0xAA85
0x0340=0xFE80
0x0341=0xCE28
0x0342=0xA8AB
0x0343=0x7E4E
0x0344=0x26A0
0x0345=0x1BA7
0x0346=0x26EF
0x0347=0x02AE
0x0348=0xFF46
0x0349=0xFD99
0x034A=0x03F0
0x034B=0xFE0F
0x034C=0xFD5F
0x034D=0x1360
0x034E=0xFB95
0x034F=0xFD36
0x0350=0x0B17
0x0351=0xF39B
0x0352=0xFD21
0x0353=0x47F3
0x0354=0x47F3
0x0355=0xE7AC
0x0356=0x4EC1
0x0357=0x0B17
0x0358=0xA80A
0x0359=0xFB95
0x035A=0x060B
0x035B=0xFD5F
0x035C=0xFE0F
0x035D=0x03F0
0x035E=0xFD99
0x035F=0xFF46
0x0360=0x02AE
0x0361=0x5542
0x0362=0x067D
0x0363=0x01CE
0x0364=0xFE2E
0x0365=0xC28A
0x0366=0xB144
0x0367=0xFE80
0x0380=0x0091
0x0381=0x6C20
0x0382=0xFED1
0x0383=0x00A6
0x0384=0x58A7
0x0385=0xFF1C
0x0386=0x00A4
0x0387=0x0015
0x0388=0x50AF
0x0389=0x299A
0x038A=0xFFEF
0x038B=0xFF97
0x038C=0x007C
0x038D=0xFFD9
0x038E=0x851A
0x038F=0x3FCC
0x0390=0xFFD0
0x0391=0xFFE4
0x0392=0x0045
0x0393=0xFFD1
0x0394=0xA1A9
0x0395=0x25F8
0x0396=0xFFD8
0x0397=0x0005
0x0398=0x001A
0x0399=0xFFE1
0x039A=0x3550
0x039B=0x000C
0x039C=0xFFEB
0x039D=0x000C
0x039E=0x0002
0x039F=0x1E8E
0x03A0=0x22AB
0x03A1=0xFFFF
0x03A2=0xFFFC
0x03A3=0x0006
0x03A4=0xFFFD
0x03A5=0x0000
0x03A6=0x0000
0x03A7=0x1051
0x0400=0x8081
//CAPTURE : 1
//CAPSEL : 0
//CAPSEL_ADC : 0
//TSGFC_RXTSP : 0
//TSGFCW_RXTSP : 1
//TSGDCLDQ_RXTSP : 0
//TSGDCLDI_RXTSP : 0
//TSGSWAPIQ_RXTSP : 0
//TSGMODE_RXTSP : 0
//INSEL_RXTSP : 0
//BSTART_RXTSP : 0
//EN_RXTSP : 1
0x0401=0x07FF
//GCORRQ_RXTSP : 2047
0x0402=0x07FF
//GCORRI_RXTSP : 2047
0x0403=0x0000
//HBD_OVR_RXTSP : 0
//IQCORR_RXTSP : 0
0x0404=0x0000
//HBD_DLY : 0
//DCCORR_AVG_RXTSP : 0
0x0405=0x0303
//GFIR1_L_RXTSP : 3
//GFIR1_N_RXTSP : 3
0x0406=0x0303
//GFIR2_L_RXTSP : 3
//GFIR2_N_RXTSP : 3
0x0407=0x0303
//GFIR3_L_RXTSP : 3
//GFIR3_N_RXTSP : 3
0x0408=0x0000
//AGC_K_RXTSP : 0
0x0409=0x0000
//AGC_ADESIRED_RXTSP : 0
0x040A=0x2000
//RSSI_MODE : 0
//AGC_MODE_RXTSP : 2
//AGC_AVG_RXTSP : 0
0x040B=0xAAAA
//DC_REG_RXTSP : 43690
0x040C=0x00F8
//CMIX_GAIN_RXTSP : 0
//CMIX_SC_RXTSP : 0
//CMIX_BYP_RXTSP : 1
//AGC_BYP_RXTSP : 1
//GFIR3_BYP_RXTSP : 1
//GFIR2_BYP_RXTSP : 1
//GFIR1_BYP_RXTSP : 1
//DC_BYP_RXTSP : 0
//GC_BYP_RXTSP : 0
//PH_BYP_RXTSP : 0
//CMIX_GAIN_RXTSP_R3 : 0
//DCLOOP_STOP : 0
0x040D=0x0000
0x040E=0x0000
//CAPD : 0
0x040F=0x0000
0x0440=0x0020
//DTHBIT_RX : 1
//SEL_RX : 0
//MODE_RX : 0
0x0441=0x0000
0x0442=0x0000
0x0443=0x0000
0x0444=0x0000
0x0445=0x0000
0x0446=0x0000
0x0447=0x0000
0x0448=0x0000
0x0449=0x0000
0x044A=0x0000
0x044B=0x0000
0x044C=0x0000
0x044D=0x0000
0x044E=0x0000
0x044F=0x0000
0x0450=0x0000
0x0451=0x0000
0x0452=0x0000
0x0453=0x0000
0x0454=0x0000
0x0455=0x0000
0x0456=0x0000
0x0457=0x0000
0x0458=0x0000
0x0459=0x0000
0x045A=0x0000
0x045B=0x0000
0x045C=0x0000
0x045D=0x0000
0x045E=0x0000
0x045F=0x0000
0x0460=0x0000
0x0461=0x0000
0x0480=0xFED8
0x0481=0x02FC
0x0482=0xFBA2
0x0483=0x038D
0x0484=0x0000
0x0485=0x0000
0x0486=0x0000
0x0487=0x0000
0x0488=0x007B
0x0489=0xF960
0x048A=0x0B32
0x048B=0xF728
0x048C=0x0000
0x048D=0x0000
0x048E=0x0000
0x048F=0x0000
0x0490=0xF8AC
0x0491=0x49EF
0x0492=0x49EF
0x0493=0xF8AC
0x0494=0x0000
0x0495=0x0000
0x0496=0x0000
0x0497=0x0000
0x0498=0xF728
0x0499=0x0B32
0x049A=0xF960
0x049B=0x007B
0x049C=0x0000
0x049D=0x0000
0x049E=0x0000
0x049F=0x0000
0x04A0=0x038D
0x04A1=0xFBA2
0x04A2=0x02FC
0x04A3=0xFED8
0x04A4=0x0000
0x04A5=0x0000
0x04A6=0x0000
0x04A7=0x0000
0x04C0=0xFED8
0x04C1=0x02FC
0x04C2=0xFBA2
0x04C3=0x038D
0x04C4=0x0000
0x04C5=0x0000
0x04C6=0x0000
0x04C7=0x0000
0x04C8=0x007B
0x04C9=0xF960
0x04CA=0x0B32
0x04CB=0xF728
0x04CC=0x0000
0x04CD=0x0000
0x04CE=0x0000
0x04CF=0x0000
0x04D0=0xF8AC
0x04D1=0x49EF
0x04D2=0x49EF
0x04D3=0xF8AC
0x04D4=0x0000
0x04D5=0x0000
0x04D6=0x0000
0x04D7=0x0000
0x04D8=0xF728
0x04D9=0x0B32
0x04DA=0xF960
0x04DB=0x007B
0x04DC=0x0000
0x04DD=0x0000
0x04DE=0x0000
0x04DF=0x0000
0x04E0=0x038D
0x04E1=0xFBA2
0x04E2=0x02FC
0x04E3=0xFED8
0x04E4=0x0000
0x04E5=0x0000
0x04E6=0x0000
0x04E7=0x0000
0x0500=0xFFEA
0x0501=0x004A
0x0502=0xFF80
0x0503=0x0085
0x0504=0x0000
0x0505=0x0000
0x0506=0x0000
0x0507=0x0000
0x0508=0xFFCB
0x0509=0xFFA9
0x050A=0x00C4
0x050B=0xFF58
0x050C=0x0000
0x050D=0x0000
0x050E=0x0000
0x050F=0x0000
0x0510=0xFFF4
0x0511=0x00E5
0x0512=0xFEDA
0x0513=0x006B
0x0514=0x0000
0x0515=0x0000
0x0516=0x0000
0x0517=0x0000
0x0518=0x00DF
0x0519=0xFE52
0x051A=0x011F
0x051B=0x009F
0x051C=0x0000
0x051D=0x0000
0x051E=0x0000
0x051F=0x0000
0x0520=0xFDC8
0x0521=0x021F
0x0522=0x0004
0x0523=0xFD47
0x0524=0x0000
0x0525=0x0000
0x0526=0x0000
0x0527=0x0000
0x0540=0x0391
0x0541=0xFED1
0x0542=0xFCD9
0x0543=0x05E7
0x0544=0x0000
0x0545=0x0000
0x0546=0x0000
0x0547=0x0000
0x0548=0xFC46
0x0549=0xFC8A
0x054A=0x0B32
0x054B=0xF428
0x054C=0x0000
0x054D=0x0000
0x054E=0x0000
0x054F=0x0000
0x0550=0xFC60
0x0551=0x484B
0x0552=0x484B
0x0553=0xFC60
0x0554=0x0000
0x0555=0x0000
0x0556=0x0000
0x0557=0x0000
0x0558=0xF428
0x0559=0x0B32
0x055A=0xFC8A
0x055B=0xFC46
0x055C=0x0000
0x055D=0x0000
0x055E=0x0000
0x055F=0x0000
0x0560=0x05E7
0x0561=0xFCD9
0x0562=0xFED1
0x0563=0x0391
0x0564=0x0000
0x0565=0x0000
0x0566=0x0000
0x0567=0x0000
0x0580=0xFD47
0x0581=0x0004
0x0582=0x021F
0x0583=0xFDC8
0x0584=0x0000
0x0585=0x0000
0x0586=0x0000
0x0587=0x0000
0x0588=0x009F
0x0589=0x011F
0x058A=0xFE52
0x058B=0x00DF
0x058C=0x0000
0x058D=0x0000
0x058E=0x0000
0x058F=0x0000
0x0590=0x006B
0x0591=0xFEDA
0x0592=0x00E5
0x0593=0xFFF4
0x0594=0x0000
0x0595=0x0000
0x0596=0x0000
0x0597=0x0000
0x0598=0xFF58
0x0599=0x00C4
0x059A=0xFFA9
0x059B=0xFFCB
0x059C=0x0000
0x059D=0x0000
0x059E=0x0000
0x059F=0x0000
0x05A0=0x0085
0x05A1=0xFF80
0x05A2=0x004A
0x05A3=0xFFEA
0x05A4=0x0000
0x05A5=0x0000
0x05A6=0x0000
0x05A7=0x0000
0x05C0=0x00FF
//DCMODE : 0
//PD_DCDAC_RXB : 1
//PD_DCDAC_RXA : 1
//PD_DCDAC_TXB : 1
//PD_DCDAC_TXA : 1
//PD_DCCMP_RXB : 1
//PD_DCCMP_RXA : 1
//PD_DCCMP_TXB : 1
//PD_DCCMP_TXA : 1
//DCMODE : 0
//PD_DCDAC_RXB : 1
//PD_DCDAC_RXA : 1
//PD_DCDAC_TXB : 1
//PD_DCDAC_TXA : 1
//PD_DCCMP_RXB : 1
//PD_DCCMP_RXA : 1
//PD_DCCMP_TXB : 1
//PD_DCCMP_TXA : 1
0x05C1=0x0000
//DCCAL_CALSTATUS_RXBQ : 0
//DCCAL_CALSTATUS_RXBI : 0
//DCCAL_CALSTATUS_RXAQ : 0
//DCCAL_CALSTATUS_RXAI : 0
//DCCAL_CALSTATUS_TXBQ : 0
//DCCAL_CALSTATUS_TXBI : 0
//DCCAL_CALSTATUS_TXAQ : 0
//DCCAL_CALSTATUS_TXAI : 0
//DCCAL_CMPSTATUS_RXBQ : 0
//DCCAL_CMPSTATUS_RXBI : 0
//DCCAL_CMPSTATUS_RXAQ : 0
//DCCAL_CMPSTATUS_RXAI : 0
//DCCAL_CMPSTATUS_TXBQ : 0
//DCCAL_CMPSTATUS_TXBI : 0
//DCCAL_CMPSTATUS_TXAQ : 0
//DCCAL_CMPSTATUS_TXAI : 0
0x05C2=0xFF00
//DCCAL_CMPCFG_RXBQ : 1
//DCCAL_CMPCFG_RXBI : 1
//DCCAL_CMPCFG_RXAQ : 1
//DCCAL_CMPCFG_RXAI : 1
//DCCAL_CMPCFG_TXBQ : 1
//DCCAL_CMPCFG_TXBI : 1
//DCCAL_CMPCFG_TXAQ : 1
//DCCAL_CMPCFG_TXAI : 1
//DCCAL_START_RXBQ : 0
//DCCAL_START_RXBI : 0
//DCCAL_START_RXAQ : 0
//DCCAL_START_RXAI : 0
//DCCAL_START_TXBQ : 0
//DCCAL_START_TXBI : 0
//DCCAL_START_TXAQ : 0
//DCCAL_START_TXAI : 0
0x05C3=0x4000
//DCWR_TXAI : 0
//DCRD_TXAI : 1
//DC_TXAI : 0
//DCWR_TXAI : 0
//DCRD_TXAI : 1
//DC_TXAI : 0
0x05C4=0x4000
//DCWR_TXAQ : 0
//DCRD_TXAQ : 1
//DC_TXAQ : 0
//DCWR_TXAQ : 0
//DCRD_TXAQ : 1
//DC_TXAQ : 0
0x05C5=0x4000
//DCWR_TXBI : 0
//DCRD_TXBI : 1
//DC_TXBI : 0
//DCWR_TXBI : 0
//DCRD_TXBI : 1
//DC_TXBI : 0
0x05C6=0x4000
//DCWR_TXBQ : 0
//DCRD_TXBQ : 1
//DC_TXBQ : 0
//DCWR_TXBQ : 0
//DCRD_TXBQ : 1
//DC_TXBQ : 0
0x05C7=0x4000
//DCWR_RXAI : 0
//DCRD_RXAI : 1
//DC_RXAI : 0
//DCWR_RXAI : 0
//DCRD_RXAI : 1
//DC_RXAI : 0
0x05C8=0x4000
//DCWR_RXAQ : 0
//DCRD_RXAQ : 1
//DC_RXAQ : 0
//DCWR_RXAQ : 0
//DCRD_RXAQ : 1
//DC_RXAQ : 0
0x05C9=0x4000
//DCWR_RXBI : 0
//DCRD_RXBI : 1
//DC_RXBI : 0
//DCWR_RXBI : 0
//DCRD_RXBI : 1
//DC_RXBI : 0
0x05CA=0x4000
//DCWR_RXBQ : 0
//DCRD_RXBQ : 1
//DC_RXBQ : 0
//DCWR_RXBQ : 0
//DCRD_RXBQ : 1
//DC_RXBQ : 0
0x05CB=0x2020
//DC_RXCDIV : 32
//DC_TXCDIV : 32
//DC_RXCDIV : 32
//DC_TXCDIV : 32
0x05CC=0x0000
//HYSCMP_RXB : 0
//HYSCMP_RXA : 0
//HYSCMP_TXB : 0
//HYSCMP_TXA : 0
//HYSCMP_RXB : 0
//HYSCMP_RXA : 0
//HYSCMP_TXB : 0
//HYSCMP_TXA : 0
0x0600=0x2000
//DAC_CLKDIV : 32
//RSSI_RSSIMODE : 0
//RSSI_PD : 0
//DAC_CLKDIV : 32
//RSSI_RSSIMODE : 0
//RSSI_PD : 0
0x0601=0x003F
//INTADC_CMPSTATUS_TEMPREF : 1
//INTADC_CMPSTATUS_TEMPVPTAT : 1
//INTADC_CMPSTATUS_RSSI2 : 1
//INTADC_CMPSTATUS_RSSI1 : 1
//INTADC_CMPSTATUS_PDET2 : 1
//INTADC_CMPSTATUS_PDET1 : 1
0x0602=0x1C00
//RSSI_BIAS : 14
//RSSI_HYSCMP : 0
//RSSI_BIAS : 14
//RSSI_HYSCMP : 0
//INTADC_CMPCFG_TEMPREF : 0
//INTADC_CMPCFG_TEMPVPTAT : 0
//INTADC_CMPCFG_RSSI2 : 0
//INTADC_CMPCFG_RSSI1 : 0
//INTADC_CMPCFG_PDET2 : 0
//INTADC_CMPCFG_PDET1 : 0
0x0603=0x00AA
//RSSI_DAC_VAL : 170
//RSSI_DAC_VAL : 170
0x0604=0xFFFF
//RSSI_PDET2_VAL : 255
//RSSI_PDET1_VAL : 255
//RSSI_PDET2_VAL : 255
//RSSI_PDET1_VAL : 4
0x0605=0x2220
//RSSI_RSSI2_VAL : 34
//RSSI_RSSI1_VAL : 32
//RSSI_RSSI2_VAL : 34
//RSSI_RSSI1_VAL : 32
0x0606=0x0909
//RSSI_TREF_VAL : 9
//RSSI_TVPTAT_VAL : 9
//RSSI_TREF_VAL : 9
//RSSI_TVPTAT_VAL : 9
0x0640=0x2AAA
//RSSIDC_CMPSTATUS : 0
//RSSIDC_RSEL : 10
//RSSIDC_HYSCMP : 5
//RSSIDC_PD : 0
//RSSIDC_CMPSTATUS : 0
//RSSIDC_RSEL : 10
//RSSIDC_HYSCMP : 5
//RSSIDC_PD : 0
0x0641=0xAAAA
//RSSIDC_DCO2 : 85
//RSSIDC_DCO1 : 42
//RSSIDC_DCO2 : 85
//RSSIDC_DCO1 : 42
[lms7002_registers_b]
0x0100=0x3409
0x0101=0x1800
0x0102=0x3180
0x0103=0x0A50
0x0104=0x0088
0x0105=0x0011
0x0106=0x318C
0x0107=0x318C
0x0108=0x410C
0x0109=0x20C0
0x010A=0x1FFF
0x010B=0x0001
0x010C=0x8865
0x010D=0x009E
0x010E=0x0000
0x010F=0x3042
0x0110=0x2B14
0x0111=0x0000
0x0112=0x2106
0x0113=0x01C1
0x0114=0x01B0
0x0115=0x0009
0x0116=0x8180
0x0117=0x2044
0x0118=0x018C
0x0119=0x528C
0x011A=0x3001
0x011C=0x8141
0x011D=0x2762
0x011E=0x0C96
0x011F=0x3602
0x0120=0xC5FF
0x0121=0x2682
0x0122=0x0FFF
0x0123=0x200F
0x0124=0x001F
0x0125=0x9400
0x0126=0x12FF
0x0200=0x0081
0x0201=0x07FF
0x0202=0x07FF
0x0203=0x0000
0x0204=0x0000
0x0205=0x070F
0x0206=0x070F
0x0207=0x070F
0x0208=0x0178
0x0209=0x0000
0x020A=0x0080
0x020B=0x4000
0x020C=0x7FFF
0x0240=0x0020
0x0241=0x0000
0x0242=0x0085
0x0243=0x5555
0x0244=0x029A
0x0245=0xAAAA
0x0246=0x0535
0x0247=0x5555
0x0248=0x07D0
0x0249=0x0000
0x024A=0x0A6A
0x024B=0xAAAA
0x024C=0x0D05
0x024D=0x5555
0x024E=0x0000
0x024F=0x0000
0x0250=0x0000
0x0251=0x0000
0x0252=0x0000
0x0253=0x0000
0x0254=0x0000
0x0255=0x0000
0x0256=0x0000
0x0257=0x0000
0x0258=0x0000
0x0259=0x0000
0x025A=0x0000
0x025B=0x0000
0x025C=0x0000
0x025D=0x0000
0x025E=0x0000
0x025F=0x0000
0x0260=0x0000
0x0261=0x0000
0x0280=0x0055
0x0281=0xFF17
0x0282=0x0162
0x0283=0xFECD
0x0284=0x001E
0x0285=0x0162
0x0286=0xFDC9
0x0287=0x016D
0x0288=0x00D2
0x0289=0xFCFD
0x028A=0x0325
0x028B=0xFF97
0x028C=0xFC5A
0x028D=0x05BD
0x028E=0xFCF3
0x028F=0xFBE7
0x0290=0x0B49
0x0291=0xF4AE
0x0292=0xFBAA
0x0293=0x489E
0x0294=0x489E
0x0295=0xFBAA
0x0296=0xF4AE
0x0297=0x0B49
0x0298=0xFBE7
0x0299=0xFCF3
0x029A=0x05BD
0x029B=0xFC5A
0x029C=0xFF97
0x029D=0x0325
0x029E=0xFCFD
0x029F=0x00D2
0x02A0=0x016D
0x02A1=0xFDC9
0x02A2=0x0162
0x02A3=0x001E
0x02A4=0xFECD
0x02A5=0x0162
0x02A6=0xFF17
0x02A7=0x0055
0x02C0=0x0055
0x02C1=0xFF17
0x02C2=0x0162
0x02C3=0xFECD
0x02C4=0x001E
0x02C5=0x0162
0x02C6=0xFDC9
0x02C7=0x016D
0x02C8=0x00D2
0x02C9=0xFCFD
0x02CA=0x0325
0x02CB=0xFF97
0x02CC=0xFC5A
0x02CD=0x05BD
0x02CE=0xFCF3
0x02CF=0xFBE7
0x02D0=0x0B49
0x02D1=0xF4AE
0x02D2=0xFBAA
0x02D3=0x489E
0x02D4=0x489E
0x02D5=0xFBAA
0x02D6=0xF4AE
0x02D7=0x0B49
0x02D8=0xFBE7
0x02D9=0xFCF3
0x02DA=0x05BD
0x02DB=0xFC5A
0x02DC=0xFF97
0x02DD=0x0325
0x02DE=0xFCFD
0x02DF=0x00D2
0x02E0=0x016D
0x02E1=0xFDC9
0x02E2=0x0162
0x02E3=0x001E
0x02E4=0xFECD
0x02E5=0x0162
0x02E6=0xFF17
0x02E7=0x0055
0x0300=0x0000
0x0301=0x0000
0x0302=0x0000
0x0303=0xFFFD
0x0304=0x0006
0x0305=0xFFFC
0x0306=0xFFFF
0x0307=0x000A
0x0308=0xFFF4
0x0309=0x0002
0x030A=0x000C
0x030B=0xFFEB
0x030C=0x000C
0x030D=0x000B
0x030E=0xFFE1
0x030F=0x001A
0x0310=0x0005
0x0311=0xFFD8
0x0312=0x002D
0x0313=0xFFF9
0x0314=0xFFD1
0x0315=0x0045
0x0316=0xFFE4
0x0317=0xFFD0
0x0318=0x0060
0x0319=0xFFC3
0x031A=0xFFD9
0x031B=0x007C
0x031C=0xFF97
0x031D=0xFFEF
0x031E=0x0094
0x031F=0xFF5F
0x0320=0x0015
0x0321=0x00A4
0x0322=0xFF1C
0x0323=0x0054
0x0324=0x00A6
0x0325=0xFED1
0x0326=0x00AE
0x0327=0x0091
0x0340=0xFE80
0x0341=0x0129
0x0342=0x005B
0x0343=0xFE2E
0x0344=0x01CE
0x0345=0xFFF7
0x0346=0xFDDF
0x0347=0x02AE
0x0348=0xFF46
0x0349=0xFD99
0x034A=0x03F0
0x034B=0xFE0F
0x034C=0xFD5F
0x034D=0x060B
0x034E=0xFB95
0x034F=0xFD36
0x0350=0x0B17
0x0351=0xF39B
0x0352=0xFD21
0x0353=0x47F3
0x0354=0x47F3
0x0355=0xFD21
0x0356=0xF39B
0x0357=0x0B17
0x0358=0xFD36
0x0359=0xFB95
0x035A=0x060B
0x035B=0xFD5F
0x035C=0xFE0F
0x035D=0x03F0
0x035E=0xFD99
0x035F=0xFF46
0x0360=0x02AE
0x0361=0xFDDF
0x0362=0xFFF7
0x0363=0x01CE
0x0364=0xFE2E
0x0365=0x005B
0x0366=0x0129
0x0367=0xFE80
0x0380=0x0091
0x0381=0x00AE
0x0382=0xFED1
0x0383=0x00A6
0x0384=0x0054
0x0385=0xFF1C
0x0386=0x00A4
0x0387=0x0015
0x0388=0xFF5F
0x0389=0x0094
0x038A=0xFFEF
0x038B=0xFF97
0x038C=0x007C
0x038D=0xFFD9
0x038E=0xFFC3
0x038F=0x0060
0x0390=0xFFD0
0x0391=0xFFE4
0x0392=0x0045
0x0393=0xFFD1
0x0394=0xFFF9
0x0395=0x002D
0x0396=0xFFD8
0x0397=0x0005
0x0398=0x001A
0x0399=0xFFE1
0x039A=0x000B
0x039B=0x000C
0x039C=0xFFEB
0x039D=0x000C
0x039E=0x0002
0x039F=0xFFF4
0x03A0=0x000A
0x03A1=0xFFFF
0x03A2=0xFFFC
0x03A3=0x0006
0x03A4=0xFFFD
0x03A5=0x0000
0x03A6=0x0000
0x03A7=0x0000
0x0400=0x8081
0x0401=0x07FF
0x0402=0x07FF
0x0403=0x0000
0x0404=0x0000
0x0405=0x0303
0x0406=0x0303
0x0407=0x0303
0x0408=0x0000
0x0409=0x0000
0x040A=0x2000
0x040B=0xAAAA
0x040C=0x00F8
0x040D=0x0000
0x040E=0x0000
0x040F=0x0000
0x0440=0x0020
0x0441=0x0000
0x0442=0x0000
0x0443=0x0000
0x0444=0x0000
0x0445=0x0000
0x0446=0x0000
0x0447=0x0000
0x0448=0x0000
0x0449=0x0000
0x044A=0x0000
0x044B=0x0000
0x044C=0x0000
0x044D=0x0000
0x044E=0x0000
0x044F=0x0000
0x0450=0x0000
0x0451=0x0000
0x0452=0x0000
0x0453=0x0000
0x0454=0x0000
0x0455=0x0000
0x0456=0x0000
0x0457=0x0000
0x0458=0x0000
0x0459=0x0000
0x045A=0x0000
0x045B=0x0000
0x045C=0x0000
0x045D=0x0000
0x045E=0x0000
0x045F=0x0000
0x0460=0x0000
0x0461=0x0000
0x0480=0xFED8
0x0481=0x02FC
0x0482=0xFBA2
0x0483=0x038D
0x0484=0x0000
0x0485=0x0000
0x0486=0x0000
0x0487=0x0000
0x0488=0x007B
0x0489=0xF960
0x048A=0x0B32
0x048B=0xF728
0x048C=0x0000
0x048D=0x0000
0x048E=0x0000
0x048F=0x0000
0x0490=0xF8AC
0x0491=0x49EF
0x0492=0x49EF
0x0493=0xF8AC
0x0494=0x0000
0x0495=0x0000
0x0496=0x0000
0x0497=0x0000
0x0498=0xF728
0x0499=0x0B32
0x049A=0xF960
0x049B=0x007B
0x049C=0x0000
0x049D=0x0000
0x049E=0x0000
0x049F=0x0000
0x04A0=0x038D
0x04A1=0xFBA2
0x04A2=0x02FC
0x04A3=0xFED8
0x04A4=0x0000
0x04A5=0x0000
0x04A6=0x0000
0x04A7=0x0000
0x04C0=0xFED8
0x04C1=0x02FC
0x04C2=0xFBA2
0x04C3=0x038D
0x04C4=0x0000
0x04C5=0x0000
0x04C6=0x0000
0x04C7=0x0000
0x04C8=0x007B
0x04C9=0xF960
0x04CA=0x0B32
0x04CB=0xF728
0x04CC=0x0000
0x04CD=0x0000
0x04CE=0x0000
0x04CF=0x0000
0x04D0=0xF8AC
0x04D1=0x49EF
0x04D2=0x49EF
0x04D3=0xF8AC
0x04D4=0x0000
0x04D5=0x0000
0x04D6=0x0000
0x04D7=0x0000
0x04D8=0xF728
0x04D9=0x0B32
0x04DA=0xF960
0x04DB=0x007B
0x04DC=0x0000
0x04DD=0x0000
0x04DE=0x0000
0x04DF=0x0000
0x04E0=0x038D
0x04E1=0xFBA2
0x04E2=0x02FC
0x04E3=0xFED8
0x04E4=0x0000
0x04E5=0x0000
0x04E6=0x0000
0x04E7=0x0000
0x0500=0xFFEA
0x0501=0x004A
0x0502=0xFF80
0x0503=0x0085
0x0504=0x0000
0x0505=0x0000
0x0506=0x0000
0x0507=0x0000
0x0508=0xFFCB
0x0509=0xFFA9
0x050A=0x00C4
0x050B=0xFF58
0x050C=0x0000
0x050D=0x0000
0x050E=0x0000
0x050F=0x0000
0x0510=0xFFF4
0x0511=0x00E5
0x0512=0xFEDA
0x0513=0x006B
0x0514=0x0000
0x0515=0x0000
0x0516=0x0000
0x0517=0x0000
0x0518=0x00DF
0x0519=0xFE52
0x051A=0x011F
0x051B=0x009F
0x051C=0x0000
0x051D=0x0000
0x051E=0x0000
0x051F=0x0000
0x0520=0xFDC8
0x0521=0x021F
0x0522=0x0004
0x0523=0xFD47
0x0524=0x0000
0x0525=0x0000
0x0526=0x0000
0x0527=0x0000
0x0540=0x0391
0x0541=0xFED1
0x0542=0xFCD9
0x0543=0x05E7
0x0544=0x0000
0x0545=0x0000
0x0546=0x0000
0x0547=0x0000
0x0548=0xFC46
0x0549=0xFC8A
0x054A=0x0B32
0x054B=0xF428
0x054C=0x0000
0x054D=0x0000
0x054E=0x0000
0x054F=0x0000
0x0550=0xFC60
0x0551=0x484B
0x0552=0x484B
0x0553=0xFC60
0x0554=0x0000
0x0555=0x0000
0x0556=0x0000
0x0557=0x0000
0x0558=0xF428
0x0559=0x0B32
0x055A=0xFC8A
0x055B=0xFC46
0x055C=0x0000
0x055D=0x0000
0x055E=0x0000
0x055F=0x0000
0x0560=0x05E7
0x0561=0xFCD9
0x0562=0xFED1
0x0563=0x0391
0x0564=0x0000
0x0565=0x0000
0x0566=0x0000
0x0567=0x0000
0x0580=0xFD47
0x0581=0x0004
0x0582=0x021F
0x0583=0xFDC8
0x0584=0x0000
0x0585=0x0000
0x0586=0x0000
0x0587=0x0000
0x0588=0x009F
0x0589=0x011F
0x058A=0xFE52
0x058B=0x00DF
0x058C=0x0000
0x058D=0x0000
0x058E=0x0000
0x058F=0x0000
0x0590=0x006B
0x0591=0xFEDA
0x0592=0x00E5
0x0593=0xFFF4
0x0594=0x0000
0x0595=0x0000
0x0596=0x0000
0x0597=0x0000
0x0598=0xFF58
0x0599=0x00C4
0x059A=0xFFA9
0x059B=0xFFCB
0x059C=0x0000
0x059D=0x0000
0x059E=0x0000
0x059F=0x0000
0x05A0=0x0085
0x05A1=0xFF80
0x05A2=0x004A
0x05A3=0xFFEA
0x05A4=0x0000
0x05A5=0x0000
0x05A6=0x0000
0x05A7=0x0000
0x0600=0x2000
0x0601=0x003F
0x0602=0x1C00
0x0603=0x00AA
0x0604=0xFFFF
0x0605=0x2220
0x0606=0x0909
0x0640=0x2AAA
0x0641=0xAAAA
[reference_clocks]
sxt_ref_clk_mhz=26
sxr_ref_clk_mhz=26

1 Like

Hi @mateusm ,

Can i know what’s the Amarisoft version you are running on ?
We are using the 2023-12-15 version but the trx driver seems to be developped with the latest 2024-06-15 API version and I don’t manage to got it working.

Thank you.

I’ve added back in the obsolete amarisoft API functions 759162064c, so now the plugin should be backwards compatible.

Thanks a lot for your work.
However, I still have the same segfault with limesuiteng_trx_get_abs_rx_power_func function.
Here is the trace :

 gdb --args ./lteenb-avx2 config/enb.cfg
GNU gdb (Ubuntu 15.0.50.20240403-0ubuntu1) 15.0.50.20240403-git
Copyright (C) 2024 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
    <http://www.gnu.org/software/gdb/documentation/>.

For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from ./lteenb-avx2...
(No debugging symbols found in ./lteenb-avx2)
(gdb) r
Starting program: /opt/amarisoft/lteenb-linux-2023-12-15/lteenb-avx2 config/enb.cfg
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
Base Station version 2023-12-15, Copyright (C) 2012-2023 Amarisoft
This software is licensed to Weaccess Group.
Support and software update available until 2024-01-13.

[New Thread 0x7ffff46006c0 (LWP 278374)]
warning: could not find '.gnu_debugaltlink' file for /lib/x86_64-linux-gnu/libcap.so.2
[New Thread 0x7ffff20006c0 (LWP 278375)]
[New Thread 0x7ffff16006c0 (LWP 278376)]
[Thread 0x7ffff16006c0 (LWP 278376) exited]
[Thread 0x7ffff20006c0 (LWP 278375) exited]
[New Thread 0x7ffff20006c0 (LWP 278377)]
[New Thread 0x7ffff16006c0 (LWP 278378)]
[Thread 0x7ffff16006c0 (LWP 278378) exited]
[Thread 0x7ffff20006c0 (LWP 278377) exited]
[Detaching after vfork from child process 278379]
Available devices:
        "LimeSDR XTRX, media=PCIe, addr=/dev/limepcie0, serial=000000008f6ac8bc"
[New Thread 0x7ffff20006c0 (LWP 278381)]
[New Thread 0x7ffff16006c0 (LWP 278382)]
[Thread 0x7ffff16006c0 (LWP 278382) exited]
[Thread 0x7ffff20006c0 (LWP 278381) exited]
[New Thread 0x7ffff20006c0 (LWP 278383)]
[New Thread 0x7ffff16006c0 (LWP 278384)]
[Thread 0x7ffff16006c0 (LWP 278384) exited]
[Thread 0x7ffff20006c0 (LWP 278383) exited]
[Detaching after vfork from child process 278385]
[Detaching after vfork from child process 278387]
[Detaching after vfork from child process 278389]
Connected: LimeSDR XTRX, media=PCIe, addr=/dev/limepcie0, serial=000000008f6ac8bc
Enable FPGA registers cache: false
Port[0] Trying sample rates which are bandwidth(4500000) * 1.536 = 6912000.000000
        Port[0] Trying sample rate : bandwidth(4500000) sample_rate(3840000)
        Port[0] Trying sample rate : bandwidth(4500000) sample_rate(7680000)
Port[0] Automatic sample rate: 7.68 MSps, n = [4] * 1.92e6
RF0: sample_rate=7.680 MHz dl_freq=2680.000 MHz ul_freq=2560.000 MHz (band 7) dl_ant=1 ul_ant=1
[New Thread 0x7ffff20006c0 (LWP 278391)]
[New Thread 0x7ffff16006c0 (LWP 278392)]
[New Thread 0x7fffeb6006c0 (LWP 278393)]
[New Thread 0x7fffe94006c0 (LWP 278394)]
[New Thread 0x7fffdce006c0 (LWP 278395)]
[New Thread 0x7fffd3e006c0 (LWP 278396)]
[New Thread 0x7fffd2c006c0 (LWP 278397)]
Hardware expected samples count in Tx packet : 8192

Thread 1 "lteenb-avx2" received signal SIGSEGV, Segmentation fault.
0x00007ffff7ed3625 in limesuiteng_trx_get_abs_rx_power_func(TRXState*, float*, int) () from /opt/amarisoft/lteenb-linux-2023-12-15/trx_limesuite.so
(gdb) bt full
#0  0x00007ffff7ed3625 in limesuiteng_trx_get_abs_rx_power_func(TRXState*, float*, int) () from /opt/amarisoft/lteenb-linux-2023-12-15/trx_limesuite.so
No symbol table info available.
#1  0x00000000004aa29f in ?? ()
No symbol table info available.
#2  0x00000000004fe1dc in ?? ()
No symbol table info available.
#3  0x00000000005cee1c in ?? ()
No symbol table info available.
#4  0x0000000000408cfe in ?? ()
No symbol table info available.
#5  0x00007ffff782a1ca in __libc_start_call_main (main=main@entry=0x408c10, argc=argc@entry=2, argv=argv@entry=0x7fffffffe448) at ../sysdeps/nptl/libc_start_call_main.h:58
        self = <optimized out>
        result = <optimized out>
        unwind_buf = {cancel_jmp_buf = {{jmp_buf = {140737488348232, -4985034530563175928, 2, 0, 0, 140737354125312, -4985034530552690168, -4985052150741874168}, mask_was_saved = 0}}, priv = {pad = {0x0, 0x0, 0x2, 0x0}, data = {prev = 0x0, cleanup = 0x0, canceltype = 2}}}
        not_first_call = <optimized out>
#6  0x00007ffff782a28b in __libc_start_main_impl (main=0x408c10, argc=2, argv=0x7fffffffe448, init=<optimized out>, fini=<optimized out>, rtld_fini=<optimized out>, stack_end=0x7fffffffe438) at ../csu/libc-start.c:360
No locals.
#7  0x0000000000408dde in ?? ()
No symbol table info available.
(gdb)

with the following rf driver config :

    name: "limesuite", // name of the plugin library trx_name.so
    logLevel: 5, // OPTIONAL, enable printing of additional information: 0-critical, (default)1-error, 2-warning, 3-info, 4-verbose, 5-debug

    // port%i represents logical samples streaming cell, it can be a single device, or aggregate of many devices
    port0: "dev0",
    // port0: "dev0,dev1,dev2"

    //port0_ini: "xtrx.ini", // OPTIONAL, will use defaults settings as base.
    port0_lpf_bandwidth_scale: 1.0, // OPTIONAL, multiplier for requested LPF bandwidth, default 1.0
    port0_max_channels_to_use: 2, // OPTIONAL, how many channels to use from each device, be default all channels are allowed
    port0_double_freq_conversion_to_lower_side: 0, // OPTIONAL, negate Q samples
    port0_linkFormat: "I16", // OPTIONAL, data transfer format to hardware: I12, I16
    // port0_syncPPS: 1, // OPTIONAL, start sampling on next PPS, default 0

    port0_rx_path: "LNAH",
    port0_tx_path: "BAND1",
    port0_rx_oversample: 0, // OPTIONAL, by default 0 (automatic max available oversample), 1, 2, 4, 8...
    port0_tx_oversample: 0, // OPTIONAL, by default 0 (automatic max available oversample), 1, 2, 4, 8...
    port0_rx_gfir_enable: 0, // OPTIONAL, by default 0
    //port0_rx_gfir_bandwidth: 5e6, // OPTIONAL, by default is set to host's expected bandwidth
    port0_tx_gfir_enable: 0, // OPTIONAL, by default 0
    //port0_tx_gfir_bandwidth: 5e6, // OPTIONAL, by default is set to host's expected bandwidth

    port0_rx_power_dBm: 0+14, // OPTIONAL, hint about absolute RX power in dBm, assuming a square signal of maximum amplitude
    port0_tx_power_dBm: 0+14, // OPTIONAL, hint about absolute TX power in dBm, assuming a square signal of maximum amplitude

    dev0_rx_calibration: "none", // all, none, filter, dciq
    dev0_tx_calibration: "none", // all, none, filter, dciq

    //port0_rx_lo_override: 1.9e6, // OPTIONAL, force set RxLO frequency
    //port0_tx_lo_override: 2.0e6, // OPTIONAL, force set TxLO frequency


    // dev%i represents individual RF SOC configuration, each device can optionally override parameters that are passed from it's respective port
    dev0: "/dev/limepcie0", // OPTIONAL, handle of which device to use, will use first available device if not specified
    //dev0_chip_index: 0, // OPTIONAL, will use 0 if not specified

    //dev0_ch0_pa_dac: 65535, // OPTIONAL, PA DAC value

    //dev0_writeRegisters: "AAAABBBB;CCCCDDDD"; // OPTIONAL, 32bit(16:addr, 16:data) SPI values to be written to FPGA
},
tx_time_offset: -100, /* normally slightly negative*/
tx_pad_duration: 30, //40
rx_ta_offset: 22, //24, 26 max
tx_gain: 50.0, /* TX gain (in dB) */
rx_gain: 17.0, /* RX gain (in dB) */

The segfault seems to be caused by this line, but I don’t know how to debug more :

LimePluginContext* lime = static_cast<LimePluginContext*>(s1->opaque);

Thanks for your help.

Fixed 9f4372e and tested with amarisoft 2023-12-15

Thank you a lot, it’s working fine now.

Sorry to reopen this thread, but after updating limesuite, I’m getting the following error when starting amarisoft:

Unsupported bandwidth: 38160000. Try to use manual sample rate configuration.

Is there any way to manually configure the sample rate? I tried something like dev0_sample_rate but was unsuccessful.

Could you give more information what you’re trying to do? Versions of LimeSuiteNG and amarisoft you’re using? Which board are you using?

That message is coming from amarisoft, so I’m not sure if the bandwidth number is coming from your configuration of from somewhere else. Are you trying to use non standard bandwidth?

At this moment there is no LimeSuiteNG parameter to override the sampling rate.

I’m using the LimeSuiteNG with the commit Fix Fairwaves XTRX rev.5 default LMS7002M register values. · myriadrf/LimeSuiteNG@a935d96 · GitHub and Amarisoft 2024-06-15. I’m using the Fairwaves XTRX rev 5.

I’m just trying to run a gNB (strangely, with an old version of LimeSuiteNG it was at least possible to run amarisoft, now this message appears and the amarisoft stops).

My configuration files (the rf_driver section) is:

rf_driver: {
    name: "limesuite", 
    logLevel: 5,

    port0: "dev0",    
    port0_rx_path: "LNAH",
    port0_tx_path: "BAND1",
    dev0_rx_calibration: "all", 
    dev0_tx_calibration: "all", 
},
  tx_time_offset: -72, 
  tx_pad_duration: 30, 
  rx_ta_offset: 22, 
  tx_gain: 70.0,
  rx_gain: 47.0, 

I’m using a bandwidth of 40 MHz

could you post your gNB conf file?

I’m running the gnb-sa.cfg config (just changing the radio section):

#define NR_TDD               1   // Values: 0 (NR FDD), 1(NR TDD)
#define FR2                  0   // Values: 0 (FR1), 1 (FR2)
#if FR2
#define UDC_TYPE             1   // Values: 0 (NO UDC), 1 (B2), 2 (A2), 3 (B4)  (refer to application note to identify your UDC type)
#define NR_TDD_CONFIG        10  // Values: FR1: 1, 2, 3, 4 (compatible with LTE TDD config 2) FR2: 10
#define NR_BANDWIDTH         100 // NR cell bandwidth
#define IF_ATTENUATION       -9  // Value: 10*log10(N_PORTS_COMBINER) + external evenutal IF attenuators
#else
#define NR_TDD_CONFIG        2   // Values: FR1: 1, 2, 3, 4 (compatible with LTE TDD config 2) FR2: 10
#define NR_BANDWIDTH         40  // NR cell bandwidth
#endif
#define N_ANTENNA_DL         1   // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4)
#define N_ANTENNA_UL         1   // Values: 1, 2, 4
#define NR_LONG_PUCCH_FORMAT 2   // Values: 2, 3, 4

/* define to 1 to enable periodic SRS with N_ANTENNA_UL ports. Uplink
   SU-MIMO is also enabled if N_ANTENNA_UL >= 2. Not all UEs support
   uplink SU-MIMO. */
#define USE_SRS             0

{
  //log_options: "all.level=debug,all.max_size=1",
  log_options: "all.level=error,all.max_size=0,nas.level=debug,nas.max_size=1,ngap.level=debug,ngap.max_size=1,xnap.level=debug,xnap.max_size=1,rrc.level=debug,rrc.max_size=1",

  log_filename: "/tmp/gnb0.log",

  /* Enable remote API and Web interface */
  com_addr: "[::]:9001",

rf_driver: {
    name: "limesuite", 
    logLevel: 5,

    port0: "dev0",    
    port0_rx_path: "LNAH",
    port0_tx_path: "BAND1",
    dev0_rx_calibration: "all", 
    dev0_tx_calibration: "all", 
},
  tx_time_offset: -72, 
  tx_pad_duration: 30, 
  rx_ta_offset: 22, 
  tx_gain: 70.0,
  rx_gain: 47.0, 

#if FR2 == 1
  udc_ports: [
  {
    #if UDC_TYPE == 1  // B2 type
       #if N_ANTENNA_DL == 1  
          args: "/dev/ttyUSB0",
       #elif N_ANTENNA_DL == 2
          args: "/dev/ttyUSB0;/dev/ttyUSB1",
       #else    
          #error Unsupported number of MIMO layers in FR2
       #endif 
    #elif UDC_TYPE == 2  // A2 type
       #if N_ANTENNA_DL == 1
          args: "/dev/ttyACM0",
       #elif N_ANTENNA_DL == 2
          args: "/dev/ttyACM0;/dev/ttyACM1",
       #else
        #error Unsupported number of MIMO layers in FR2
       #endif
    #elif UDC_TYPE == 3  // B4 type
        args: "/dev/ttyUSB0",
    #else
       #warning No UDC used for FR2 testing
    #endif

    cmd: "udc-auto-cfg.sh",
  },
  ],
#endif

  amf_list: [
    {
      /* address of AMF for NGAP connection. Must be modified if the AMF runs on a different host. */
      amf_addr: "127.0.1.100",
    },
  ],
  /* GTP bind address (=address of the ethernet interface connected to
     the AMF). Must be modified if the AMF runs on a different host. */
  gtp_addr: "127.0.1.1",
#ifdef GTP_U_BUNDLING
  gtp_use_packet_bundling: true,
#endif

  gnb_id_bits: 28,
  gnb_id: 0x12345,

  en_dc_support: true,

  rf_ports: [
    {
#if FR2
       udc_port: 0,
       tx_power_offset:IF_ATTENUATION,
#endif
    },
  ],

  /* list of cells */
  cell_list: [],

  nr_cell_list: [
  {
    rf_port: 0,
    cell_id: 0x01,
#if NR_TDD == 1
#if FR2
    band: 257,
    dl_nr_arfcn: 2079167,  /* 28000.08 MHz */
    subcarrier_spacing: 120, /* kHz */
    ssb_pos_bitmap: "0100000000000000000000000000000000000000000000000000000000000000",

    rx_to_tx_latency: 9, /* slots */
#else
    band: 78,
    dl_nr_arfcn: 632628,  /* 3489.42 MHz */
    subcarrier_spacing: 30, /* kHz */
    ssb_pos_bitmap: "10000000",
#endif
#else
    band: 7,
    dl_nr_arfcn: 531000,  /* 2680 MHz */
    subcarrier_spacing: 15, /* kHz */
    ssb_pos_bitmap: "1000",
#endif
  },
  ], /* nr_cell_list */

  nr_cell_default: {
    bandwidth: NR_BANDWIDTH, /* MHz */
    n_antenna_dl: N_ANTENNA_DL,
    n_antenna_ul: N_ANTENNA_UL,

    /* force the timing TA offset (optional) */
//    n_timing_advance_offset: 39936,
    /* subframe offset to align with the LTE TDD pattern (optional) */
//    subframe_offset: 2,

#if NR_TDD == 1
    tdd_ul_dl_config: {
#if NR_TDD_CONFIG == 1
      pattern1: {
        period: 5, /* in ms */
        dl_slots: 7,
        dl_symbols: /* 6 */ 2,
        ul_slots: 2,
        ul_symbols: 2,
      },
#elif NR_TDD_CONFIG == 2
      pattern1: {
        period: 5, /* in ms */
        dl_slots: 7,
        dl_symbols: 6,
        ul_slots: 2,
        ul_symbols: 4,
      },
#elif NR_TDD_CONFIG == 3
      pattern1: {
        period: 5, /* in ms */
        dl_slots: 6,
        dl_symbols: 2,
        ul_slots: 3,
        ul_symbols: 2,
      },
#elif NR_TDD_CONFIG == 4
      pattern1: {
        period: 3, /* in ms */
        dl_slots: 3,
        dl_symbols: 6,
        ul_symbols: 4,
        ul_slots: 2,
      },
      pattern2: {
        period: 2, /* in ms */
        dl_slots: 4,
        dl_symbols: 0,
        ul_symbols: 0,
        ul_slots: 0,
      },
#elif NR_TDD_CONFIG == 10
      /* only for FR2 */
      pattern1: {
        period: 0.625, /* in ms */
        dl_slots: 3,
        dl_symbols: 10,
        ul_slots: 1,
        ul_symbols: 2,
      },
#endif
    },
#endif
    ssb_period: 20, /* in ms */
    n_id_cell: 500,

    plmn_list: [ {
      tac: 100,
      plmn: "00101",
      reserved: false,
      nssai: [
        {
         sst: 1,
        },
        /*{
         sst: 2,
        },
        {
         sst: 3,
         sd: 50,
        },*/
       ],
      },
    ],

    /*sib_sched_list: [
      {
        filename: "sib2_nr.asn",
        si_periodicity: 16,
      },
      {
        filename: "sib3_nr.asn",
        si_periodicity: 16,
      },
      {
        filename: "sib4_nr.asn",
        si_periodicity: 32,
      },
    ],
    sib9: {
      si_periodicity: 32
    },*/
    si_window_length: 40,

    cell_barred: false,
    intra_freq_reselection: true,
    q_rx_lev_min: -70,
    q_qual_min: -20,
    //p_max: 10, /* dBm */

    root_sequence_index: 1, /* PRACH root sequence index */

    /* Scheduling request period (slots). */
    sr_period: 40,

    dmrs_type_a_pos: 2,

    /* to limit the number of HARQ feedback in UL, use pdsch_harq_ack_max;
       allows to workaround issues with SM-G977N for example */
    //pdsch_harq_ack_max: 2,

    prach: {
#if NR_TDD == 1
#if FR2
      prach_config_index: 149, /* format C0, every 4 frames */
      msg1_subcarrier_spacing: 120, /* kHz */
#else
#if NR_TDD_CONFIG == 4
      prach_config_index: 156, /* format B4, subframe 2 */
#else
      prach_config_index: 160, /* format B4, subframe 9 */
#endif
      msg1_subcarrier_spacing: 30, /* kHz */
#endif
#else
      prach_config_index: 16, /* subframe 1 every frame */
#endif
      msg1_fdm: 1,
      msg1_frequency_start: -1,
      zero_correlation_zone_config: 15,
      preamble_received_target_power: -110, /* in dBm */
      preamble_trans_max: 7,
      power_ramping_step: 4, /* in dB */
#if FR2 == 1
      ra_response_window: 40, /* in slots */
#elif NR_TDD == 1
      ra_response_window: 20, /* in slots */
#else
      ra_response_window: 10, /* in slots */
#endif
      restricted_set_config: "unrestricted_set",
      ra_contention_resolution_timer: 64, /* in ms */
      ssb_per_prach_occasion: 1,
      cb_preambles_per_ssb: 8,
    },

    pdcch: {
      search_space0_index: 0,

      dedicated_coreset: {
        rb_start: -1, /* -1 to have the maximum bandwidth */
        l_crb: -1, /* -1 means all the bandwidth */
        duration: 0, /* 0 means to automatically set it from the coreset bandwidth */
        precoder_granularity: "sameAsREG_bundle",
      },

      css: {
        n_candidates: [ 0, 0, 4, 0, 0 ],
      },
      rar_al_index: 2,
      si_al_index: 2,

      uss: {
        n_candidates: [ 0, 4, 0, 0, 0 ],
        dci_0_1_and_1_1: true,
      },
      al_index: 1,
    },

#if FR2
    k_min: 8,
#endif
    pdsch: {
      mapping_type: "typeA",
      dmrs_add_pos: 1,
      dmrs_type: 1,
      dmrs_max_len: 1,
      /* k0 delay in slots from DCI to PDSCH: automatic setting */
      /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
      mcs_table: "qam256",
      rar_mcs: 2,
      si_mcs: 6,
      /* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed
       * based on DL channel quality estimation */
      /* mcs: 24, */
    },
    
    csi_rs: {
      resource_auto: {
        nzp_csi_rs_period: 80,
#if FR2
        trs_presence: false,
#endif
      },
      csi_report_config: [
        {
          report_config_type: "periodic",
          period: 80,
        },
      ],
    },
    
    pucch: {
      pucch_group_hopping: "neither",
      hopping_id: -1, /* -1 = n_cell_id */
      p0_nominal: -96,
#if 0
        pucch0: {
          initial_cyclic_shift: 1,
          n_symb: 1,
        },
#else
        pucch1: {
          n_cs: 3,
          n_occ: 3,
          freq_hopping: true,
#if USE_SRS && NR_TDD == 0
          n_symb: 12,
#endif
        },
#endif
#if NR_LONG_PUCCH_FORMAT == 2
        pucch2: {
          n_symb: 2,
          n_prb: 1,
          freq_hopping: true,
          simultaneous_harq_ack_csi: false,
          max_code_rate: 0.25,
        },
#elif NR_LONG_PUCCH_FORMAT == 3
        pucch3: {
          bpsk: false,
          additional_dmrs: false,
          freq_hopping: true,
          n_prb: 1,
          simultaneous_harq_ack_csi: true,
          max_code_rate: 0.25,
        },
#elif NR_LONG_PUCCH_FORMAT == 4
        pucch4: {
          occ_len: 4,
          bpsk: false,
          additional_dmrs: false,
          freq_hopping: true,
          simultaneous_harq_ack_csi: true,
          max_code_rate: 0.25,
        },
#endif
    },

#if USE_SRS
    srs: {
      resource_auto: {
        codebook: {
          resource_type: "periodic",
          period: 80, /* in slots */
        }
      }
    },
#endif

    pusch: {
      mapping_type: "typeA",
      n_symb: 14,
      dmrs_add_pos: 1,
      dmrs_type: 1,
      dmrs_max_len: 1,
      tf_precoding: false,
      mcs_table: "qam256", /* without transform precoding */
      mcs_table_tp: "qam256", /* with transform precoding */
      ldpc_max_its: 5,
      /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
      p0_nominal_with_grant: -84,
      msg3_mcs: 4,
      msg3_delta_power: 0, /* in dB */
      beta_offset_ack_index: 9,
#if USE_SRS
      max_rank: N_ANTENNA_UL,
#endif

      /* if defined, force the PUSCH MCS for all UEs. Otherwise it is
       computed from the last received PUSCH. */
      /* mcs: 16, */
    },

    /* MAC configuration */
    mac_config: {
      msg3_max_harq_tx: 5,
      ul_max_harq_tx: 5, /* max number of HARQ transmissions for uplink */
      dl_max_harq_tx: 5, /* max number of HARQ transmissions for downlink */
      ul_max_consecutive_retx: 30, /* disconnect UE if reached */
      dl_max_consecutive_retx: 30, /* disconnect UE if reached */
      periodic_bsr_timer: 20,
      retx_bsr_timer: 320,
      periodic_phr_timer: 500,
      prohibit_phr_timer: 200,
      phr_tx_power_factor_change: "dB3",
      sr_prohibit_timer: 0, /* in ms, 0 to disable the timer */
      sr_trans_max: 64,
    },

    cipher_algo_pref: [],
    integ_algo_pref: [2, 1],

    inactivity_timer: 10000,

    drb_config: "drb_nr.cfg",
  },
}


Fixed in 9d371a4

Your rf_driver was not specifying which board to use as “dev0”

Thanks @ricardas! Unfortunately, now I’m getting another error:

CSW: lowest=244, highest=247, will use=245
choosing wider CSW locking range: low=244, high=247
TuneVCO(SXR) - confirmed lock with final csw=245, cmphl=2
VCOL : csw=245 tune ok
Selected: VCOL, CSW_VCO: 245
Rx DC auto   I:  14, Q:  10, (RSSI: 0x00A28)
Rx DC manual I:   6, Q:  18, (RSSI: 0x007DB)
RxTSP DC corrector enabled (RSSI: 0x0006E)
Receiver saturation search, target level: 20498 ((RSSI: 0x05012))
initial  PGA:  0, RXLOOPB:  7, (RSSI: 0x00006)
adjusted PGA:  1, RXLOOPB: 15, (RSSI: 0x00005)
Low calibration test signal level (RSSI: 0x00005), expected to be more than (RSSI: 0x00005). Calibration results might be impacted. Try re-calibrating or adjusting the TX gains.
Tx calibration failed
FPGA::SetInterfaceFreq tx:122.880 MHz rx:122.880 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 1
FPGA PLL[1] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
Retry0: SetPllFrequency
FPGA SetPllFrequency: PLL[1] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 1
FPGA PLL[1] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
Retry1: SetPllFrequency
LML RX phase search FAIL
FPGA SetPllFrequency: PLL[1] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:0 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:241.831 findPhase: 0
FPGA PLL[1] PLLRST_START
FPGA PLL[1] PLLRST_START done
FPGA PLL[1] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 1
FPGA PLL[0] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
Retry0: SetPllFrequency
FPGA SetPllFrequency: PLL[0] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:122.91 findPhase: 1
FPGA PLL[0] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
Retry1: SetPllFrequency
LML TX phase search FAIL
FPGA SetPllFrequency: PLL[0] input:122.880 MHz clockCount:2
CLK[0] Fout:122.880 MHz bypass:0 phase:0 findPhase: 0
CLK[1] Fout:122.880 MHz bypass:0 phase:0 findPhase: 0
FPGA PLL[0] PLLRST_START
FPGA PLL[0] PLLRST_START done
FPGA PLL[0] M=10, N=1, Fvco=1228.800 MHz (Requested 1228.800 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
Could not set RF driver start params
DeviceRegistry Removed: LimePCIe
DeviceRegistry Removed: FTDI
DeviceRegistry Removed: FX3

This error occurs even if I disable calibration.

It’s the FPGA gateware issue: Fix for PLL configuration hang · myriadrf/LimeSDR-XTRX_GW@1834a1d · GitHub

it’s not fixed in the XTRX rev. 5 gateware. Could possibly workaround it by reconfiguring multiple times with gradually increasing sampling rate.

Do you say to make these changes in the SetInterfaceFreq function? They would be rxRate_Hz and txRate_Hz, right?