I am a bit confused about the rate of each module in the LimeSDR.
What’s the maximum rate of CLK_H and CLK_L?
What’s the maximum rate of TxTSP and RxTSP?
What’s the relationship between the CLK_L and two TSP? Why different CLKH_OV_CLKL have different TSP rates?
Which rate represents the ADC or DAC sample rate? Is the ADC a delta-sigma architecture?
Is there a clock block diagram with maximum rates of each block of the Rx and Tx signal chain?
Thanks!
