The LMS7002M at the heart of the LimeSDR has two TX channels and two RX channels, but there is only one TX synthesizer and one RX synthesizer. So both RX channels share a common clock ? And both TX channels share a common clock. My question is how far in frequency can the two RX channels be apart and how far can the two TX channel be apart.
I’m guessing that one RX channel could not be tuned to say GPS [1575.42 MHz (10.23 MHz × 154)], to generate a GPSDO within the remaining FPGA logic while another one was being used to measure frequency shifts on the carrier in commercial broadcast FM [87.5 MHz to 108 MHz].
But is there enough to say truncate a few bits off the bottom of the of each sample within the FPGA from each RX channel to allow phase coherent wide band signal to be captured ? Say the full 80MHz of Bluetooth [1MHz x 79+1 or 2 MHz x 37+3] at 8-bits.
So my question is what are the outermost limits that the two RX channels can be tuned apart (and the same for the two TX channels) ?
I suppose ultimately what I am asking is, are the RXLO provided to RxA and RxB at the exact same frequency ? And the same for TXLO provided to TxA and TxB.
If they are the same, then am I right in saying that in the particular design of the LimeSDR having 160MHz bandwidth available through the analogue interface, of the LMS7002M, is not important from this perspective. Since in this particular design, of the LimeSDR, bandwidth is limited by the Digital interface ?
Would I be right in saying that both RxA and RxB can be tuned to any frequency from 100 kHz to 3.8 GHz but because of the common RxNCO they are limited to looking at the same 61.44MHz after the four ADC ? The TSP can digitally tune to different parts within this 61.44MHz bandwidth for both RxA and RxB with the LimeSDR board.
Or can the four (Rx) ADC’s run at 160MHz and the 60MHz is maximum output bandwidth from the TSP for RxA and/or RxB ?
I get that the limiting bottleneck, in getting data into or out of the LimeSDR board, is the USB 3.0 interface, but I’m interested as to what are the maximum data rates are within the LMS7002M chip and within the board itself.
