Using LMS6002D with low PLL Reference Clock

Dear All,

I need to use LMS6002D with a lower PLL Reference Clock (e.g. 19 MHz) than what is specified in the datasheet.
I like to know what would be the possible effects on the performance of the chip if we reduce the PLL Reference Clock frequency?


Hi @Med,

Penalty will be worse phase noise and gaps in the frequency range.

Many thanks Zack for this clearification

Hi Zack,

I am using the reference of 19.2 MHz and trying to lock the PLL to frequency of 1630 MHz, the integer divider value for this configuration NINT is 339, it seems that for the NINT values above 320, the PLL does not lock to the desired frequency.
In theory 9 bits is allocated to NINT and it can be as large as 511, but is there something related to the design of the chip that limits the maximum value of this divider?

How large are the mentioned frequency gaps in your answer?

Many thanks in advance for your help.