Hi,
I am new to LimeSDR and trying to get started. But before that, I would like to know the usage of DDR2 memory attached to FPGA. The document says: “2x1 Gbit DDR2 with 16-bit data bus. It can be used for data manipulation between transceiver and FPGA”. Following are my questions:
- Why is it needed?
- Was it mandatory or just kept in the design to have a wider scope of application? Will it be used if no data manipulation is needed at FPGA and data just needs to be passed on to FW?
- From the source, I can’t figure out the data flow between DDR2 and other system components.
Any help would be appreciated.
Thanks