Usage of DDR2 connected to FPGA

Hi,
I am new to LimeSDR and trying to get started. But before that, I would like to know the usage of DDR2 memory attached to FPGA. The document says: “2x1 Gbit DDR2 with 16-bit data bus. It can be used for data manipulation between transceiver and FPGA”. Following are my questions:

  1. Why is it needed?
  2. Was it mandatory or just kept in the design to have a wider scope of application? Will it be used if no data manipulation is needed at FPGA and data just needs to be passed on to FW?
  3. From the source, I can’t figure out the data flow between DDR2 and other system components.

Any help would be appreciated.

Thanks

Hello @gchat,

Currently it is used to play waveform just to unload PC and cut the data flow from PC to the board.[quote=“gchat, post:1, topic:1500”]
2. Was it mandatory or just kept in the design to have a wider scope of application? Will it be used if no data manipulation is needed at FPGA and data just needs to be passed on to FW?
[/quote]

It is not mandatory. LimeSDR-USB is designed to have a lot of capabilities. For instance, you do have USB2 only and want to capture a signal at high sample rate which USB2 can not handle. Hence you just pump IQ data at high sample rate to the RAM and the you just upload it at low speed to PC for further processing.

It is related to item (1) I think.

@Zack… Thanks a lot for your quick response.

Sorry didn’t understand completely. Can you please explain little bit more.

Ok. Got it. So if I am using USB3, most probably I don’t need to use DDR2, right? Also,

Do I need any code for this or handled automatically by the system?

Thanks

Using LimeSuiteGUI you may upload waveform file to RAM and then send IQ data to LMS7002M chip. For instance you may upload one period of sine wave and then play it continuously. [quote=“gchat, post:3, topic:1500”]
Ok. Got it. So if I am using USB3, most probably I don’t need to use DDR2, right?
[/quote]

It depends on the task you have to solve. Currently RAM is not involved.[quote=“gchat, post:3, topic:1500”]
Do I need any code for this or handled automatically by the system?
[/quote]

This functionality is not implemented in the current gateware (i.e. FPGA bitstream).

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I would like to delete the DDR tester but keep the waveform player.

Is it safe to delete the symbol and tie all the previously connected buses and nodes to GND?

If not, what is the best approach?

hi @gwong

You can delete ddr2_tester:inst46 symbol and all DDR2_2_* external pins from .bdf schematic. In order not to break compilation tie these signals to GND:
ddr2_2_pnf_per_bit_persisit[31…0]
ddr2_2_test_pass
ddr2_2_test_fail
ddr2_2_test_complete
Signals test_en[5], SI_CLK1, test_inject_error[5] connected to ddr2_tester:inst46 symbol can be deleted also.

Thank you @Zack!

Works a dream!

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