# TxTSPCLK / RxTSPCLK Question

Good evening,

I have a quick question regarding the LMS7002M TSP clocks for both the TX and the RX chains. What exactly are they values? I can’t seem to find the answer in the datasheet, but I’m assuming that it is either the selected sampling rate, the ref clock 30.72MHz or some frequency derivated from this last one.

In particular, I’m trying to understand what exactly does this “t” represent in the datasheet description of the CMIX:

If t = n/f_instruction , I’m just trying to understand what it is and how to control the f_instruction.

Thanks!

TSP stands for Transceiver Signal Processor, which is fully digital. So TxTSPCLK and RxTSPCLK would be mathematical NCO’s (Numerically Controlled Oscillators) for an all digital (maths) mixer. And the TSP sits after the ADC, but before the FPGA. So everything that the TSP does is maths (And it also sits before the DAC and after the FPGA, but it is easier to focus on one direction for understanding).

If the analogue tuner was tuned to it’s minimum frequency of 30MHz, then after the ADC, to get all the way down to 100kHz this happens using maths with numerical Oscillators and numerical mixers within the TSP.

So the lower limit of the RxTSPCLK frequency would be 0Hz and the upper limit would be the actual sample rate of the ADC’s. Which in most cases is going to be higher than the sample rate after the TSP, because of the decimation stage within the TSP, which will increase the dynamic range. So the minimum for the maximum would be the post TSP sample rate and the maximum for the maximum would depend on how much decimation is carried out within the TSP.