Hi @Zack,
We are now planning to do the RxTSG test to verify the interface between the LMS chip and FPGA.
Could you please advise which are the registers to be configured to implement this (starting from CGEN, port configurations, data modes etc…).
In an other post, Rx signal capture using LMS7002
you had mentioned that
1. You can not set HBD/HBI to bypass. It should be 2^1. Otherwise MCLK frequency is not correct. This is very important!
may I ask you to please elaborate.
Also, there are still two more days but may I ask if the document you mentioned is ready?
Regards,