We have made a custom board for the LMS7002M and for a multi channel system are connecting it to a Xilinx Virtex-6 FPGA. The problem is achieving timing closure.
As per the datasheet of the LMS7002M
Tsetup_min = 1ns
Thold_min = 0.2ns
which gives a window of 1.2ns which is very tight and from discussion on a Xilinx forum even the top end FPGAs would have difficulty in achieving this.
That said, the LMS7002M is already in production, numerous LimiMini and USB SDR boards are being used and that too with a normal Altera FPGA. Which means that the constraints do not need to be so tight.
May I ask you to please advise on what kind of constraints need to be used on the setup and hold times for both Tx and Rx to achieve timing closure.
Further, going through the sdc file of the Quartus project for LimeMini,
Tco_max and Tco_min are 1.05 and 2.9. Please advise on how these are measured and what do they mean in context of MIMO DDR mode interface.
LMS_LMS7_Tsu (setup) is 1.20
LMS_LMS7_Th (hold time) is 1.00
is there a typo in the datasheet?