Was finally able to get the setup ready to change the phase of the FPGA PLL output under user control. Thank you for the suggestion.
Status: Able to get clean data up till CGEN = 400MHz (with decim = 2, so DDR data out is at 200MHz with MCLK2 at 100MHz).
However when I try with CGEN = 600MHz, I am unable to get clean data for any phase shift value.
For the CGEN = 400MHz or MCLK2 = 100MHz setup, the high time of clock is 5ns and low time is 5ns.
The range of delay (using PLL) over which the data was obtained without noise is about 1.4ns.
In my understanding the available phase shift range or delay (sorry for using the terms loosely), should be close to 5ns rather than the rather low 1.4ns.
In the above figure, this range is indicated by t1 while the non-usable time is shown by delta1 and 2 (d1 and d2).
Am I missing something?
The lengths on the FPGA board are well matched and in fact the same board has been used to interface a serial LVDS ADC running at 500MHz DDR (in short, the PCB is alright).
There are three attributes which can cause the narrowing of this window:
- Jitter on the data lines
- Length mismatch in the PCB
- rise and fall times
I am ignoring the setup and hold times of the FPGA as the FPGA is a Virtex 6 FPGA which has tsu and th of the order of a few tens of ps.
We have checked the total trace length from the chip to the FPGA pins and the maximum mismatch is about 700mils which translates to about 110ps.
So either there is a lot of jitter on the data lines (DIQ2) or the rise and fall times of the data lines is quite high.
Question 1: Is the phase adjusted in the LimeMini in this way?
Problem 2: Let’s say I am able to get all the LMS ICs give out correct data using this approach (i.e., each IC needs a different phase shift (worst case scenario)).
For my application I need to combine the data (beamforming) so I how do I get them to a common clock domain while maintaining synchronization.
FIFO approach might be one but I am not clear about how it would give me consistent synchronization (not to forget repeatable across power cycles and boards).
Looking forward to your input,