Receiving DIQ2 data

#1

Hello @Zack,
As per your suggestion we are receiving DIQ2 data into the FPGA by phase shifting MCLK2 with a PLL. The phase shift is tuned by making the LMS send know bits.
The problem: the phase shift setting doesn’t work when the LMS is reprogrammed (with the same settings that were used to calibrate the interface in the first place). The LMS is not even power cycled. It is just reprogrammed.
Please advise and thank you for your time,

#2

Hello @Zack,
Looking forward to your inputs on this.
Regards,

#3

Hello @Zack,
Sorry to bother again, but we are close to our project completion and could use your valuable input.
Regards,