# Power consumption

Can anyone tell me what the typical power consumption for the board is when for example its running a simple FM demodulator?

Short answer: The upper limit is 4.5 Watts (Maximum that USB 3.0 can supply). But the power required will be less than ~ 3.082 Watts.

Since the FM demodulation is most likely going to be executing on the host computer, I do not think it would matter much what demodulation was being used. What would matter is the data rate, so if the data rate was low then Iâ€™m sure things could be in a lower power configuration than the maximum I describe below. But there would be a lower limit, which would be 1-2 watts at a guess.

Long answer: The Four main chips on the board are the LMS7002M (tuner+ADC+DAC), FPGA, 256MB of RAM and the USB 3.0 controller. I would guess that 85%-95% of the power usage would be by those 4 chips.

All USB 3.0 ports must provide a maximum of 900mA @ 5V (4.5 watts), it is in the standard.

Low power consumption, typical 550mW in full 2x2 MIMO mode (330mW in SISO mode) using external LDOs

From the â€śGeneral specificationsâ€ť table
TX supply current 200mA - At -7dBm output power, 2x2 MIMO, including the DACs and TSP
RX supply current 280mA - For 2x2 MIMO, including the ADCs and TSP
Analog supply voltage, high (1.71) 1.8 (1.89) volts
Analog supply voltage, med (1.33) 1.4 (1.47) volts
Analog supply voltage, low (1.1 ) 1.2 (1.3 ) volts

Maximum ( 1.8 x ( 0.200 + 0.280 ) ) ~= 0.864 watts

Second source: http://www.digikey.com/product-search/en/rf-if-and-rfid/rf-transceiver-ics/3540293?k=LMS7002M
RX current 420mA
TX current 350mA
Supply voltage 1.1V-1.89V
say 1.8 x 0.420 = 0.756 watts

â€” FPGA: EP4CE40F23C8N (USB) â€”
â€” FPGA: EP4CGX30CF23C7N (PCIe) â€”
Maximum Power: ~1.5W (depends on how much logic is actively switching states)
Typical ~ 150 mW power is consumption per channel
Static (minimum) ~ 110mW ( https://www.altera.com/products/fpga/cyclone-series/cyclone-iv/features/cyiv-power.html )

---- RAM 256 MBytes DDR2 SDRAM â€”
http://eu.mouser.com/search/ProductDetail.aspx?R=0virtualkey0virtualkeyAS4C64M16D2-25BIN
AS4C64M16D2 SDRAM 64M x 16-bit 1.8V 130mA (234mW each and there are two of these chips)

---- USB 3.0 controller Cypress USB 3.0 CYUSB3014-BZXC â€”
http://www.cypress.com/part/cyusb3014-bzxc
Maximum 200mA @ 1.25 volts (250mW)

If you add the all the maximum powers up you get:
250mw(USB)+1.5W(FPGA)+864mW(LMS7002M)+234mW(RAM)+234mW(RAM) = 3.082 Watts

But the above would be with all the gateware in the FPGA defined and configured to use maximum power (continuously switching), 2 TX channels running while 2 RX channels were running. The USB controller running flat out and the 256MiB of RAM being updated at maximum data rate. So for one channel RX only it should be less than this, and with a low enough data rate it should be lower still. At a guess you are probably talking somewhere more than 1 watt and less than 2 watts as the lower limit to power requirement.

Other than my guess above you will need to wait on someone with an actual LimeSDR board who happens to also own a USB 3.0 power doctor. to report back real world figuresâ€¦

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