LimeSDR XTRX PLL Clock TX Configuration Error

sens118 · 25 April 2024 17:13

Hello,

we are trying to configure the LimeXTRX with limesuiteNG.

We did some tests on the dualRXTX example and found out, that the PLL clock configuration for the TX does not succeed if the sampling rate is higher than a threshold. We found this behavior to occur upon sampling more than 20MHz. At 10MHz, no issue occurs.

We notice that RX works fine in any case, i.e., its PLL can be configured in any case regardless of the sampling frequency, while this is not the case with TX: There the PLL clock 1 is reporting some error in register 0x0021 and setting the error bits to 0x0008.

We attach the logs below for the 20MHz example. We used the provided documentation for the XTRX gateware from LimeSDR-XTRX_GW/doc/LimeSDR-XTRX_1v2_GW_User_Manual_v1.00.pdf at master · myriadrf/LimeSDR-XTRX_GW · GitHub but could not follow the output. Are we messing up with lookup in the reference?

DeviceRegistry Added: FX3
DeviceRegistry Added: FTDI
DeviceRegistry Added: LitePCIe
Devices found :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000

Configuring device ...
SetFrequencySXR, (3500.000 MHz)INT 130, FRAC 645277, DIV_LOCH 0, EN_DIV2_DIVPROG 1
Expected VCO 7000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOM : failed to lock
Tuning VCOH :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=2
csw=124 cmphl=2
csw=126 cmphl=2
csw=127 cmphl=2
adjust with linear search:
csw=119 cmphl=0
CSW: lowest=120, highest=127, will use=123
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=3
csw=144 cmphl=3
csw=136 cmphl=2
csw=140 cmphl=2
csw=142 cmphl=2
csw=143 cmphl=2
adjust with linear search:
csw=135 cmphl=2
csw=134 cmphl=2
csw=133 cmphl=2
csw=132 cmphl=2
csw=131 cmphl=2
csw=130 cmphl=2
csw=129 cmphl=2
csw=128 cmphl=2
CSW: lowest=128, highest=143, will use=135
CSW is locking in one continous range: low=120, high=143
TuneVCO(SXR) - confirmed lock with final csw=131, cmphl=2
VCOH : csw=131 tune ok
Selected: VCOH, CSW_VCO: 131
SetFrequencySXT, (3500.000 MHz)INT 130, FRAC 645277, DIV_LOCH 0, EN_DIV2_DIVPROG 1
Expected VCO 7000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOM : failed to lock
Tuning VCOH :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=2
csw=124 cmphl=2
csw=126 cmphl=2
csw=127 cmphl=2
adjust with linear search:
csw=119 cmphl=2
csw=118 cmphl=2
csw=117 cmphl=0
CSW: lowest=118, highest=127, will use=122
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=3
csw=144 cmphl=3
csw=136 cmphl=2
csw=140 cmphl=2
csw=142 cmphl=2
csw=143 cmphl=2
adjust with linear search:
csw=135 cmphl=2
csw=134 cmphl=2
csw=133 cmphl=2
csw=132 cmphl=2
csw=131 cmphl=2
csw=130 cmphl=2
csw=129 cmphl=2
csw=128 cmphl=2
CSW: lowest=128, highest=143, will use=135
CSW is locking in one continous range: low=118, high=143
TuneVCO(SXT) - confirmed lock with final csw=130, cmphl=2
VCOH : csw=130 tune ok
Selected: VCOH, CSW_VCO: 130
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 161; interval [157, 165]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 160; interval [157, 163]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
Sampling rate set(20.000 MHz): CGEN:160.000 MHz, Decim: 2^1, Interp: 2^1
INT 97, FRAC 483958, DIV_OUTCH_CGEN 7
VCO 2560.00 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 201; interval [198, 205]
Rx calibrate ch.A @ 3500 MHz, BW: 20 MHz, RF input: LNAW, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I:  35, Q:  63, -31.0 dBFS
Rx DC manual I:  34, Q:  63, -31.0 dBFS
RxTSP DC corrector enabled -34.3 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -75.012 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 62 | -30.519 dbFS
Signal strength (-30.5 dBFS) low, expected to be more than (-30.0 dBFS), loopback not working?
Rx calibration failed
Rx ch0 DC/IQ calibration failed: Loopback signal weak: not connected/insufficient gain?
Tx ch.A , BW: 20 MHz, RF output: BAND2, Gain: 63, loopb: internal
Rx DC auto   I:  34, Q:  63, -31.7 dBFS
Rx DC manual I:  26, Q:  63, -32.2 dBFS
RxTSP DC corrector enabled -76.8 dBFS
Receiver saturation search, target level: 20480 (-12.868 dBFS)
initial  PGA:  0, RXLOOPB:  7, -43.81 dbFS
adjusted PGA: 25, RXLOOPB: 15, -14.12 dBFS
Rx DC auto   I:  26, Q:  63, -6.8 dBFS
Rx DC manual I:  26, Q:  63, -6.9 dBFS
RxTSP DC corrector enabled -56.0 dBFS
#0 Tx DC manual I: -216, Q:  136, -50.9 dBFS
#1 Tx DC manual I: -272, Q:  200, -59.6 dBFS
#2 Tx DC manual I: -280, Q:  202, -59.5 dBFS
#0 Tx IQCORR: -128, -35.6 dBFS
#1 Tx GAIN_I: 1541, -44.3 dBFS
#2 Tx IQCORR: -144, -46.5 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: | -280 | 1541 | -144
Q: |  202 | 2047 |
Calibrate Tx duration: 463 ms
Rx calibrate ch.B @ 3500 MHz, BW: 20 MHz, RF input: LNAW, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I:   0, Q:  63, -21.2 dBFS
Rx DC manual I:  -8, Q:  63, -21.9 dBFS
RxTSP DC corrector enabled -71.5 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -78.267 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 62 | -33.836 dbFS
Signal strength (-33.8 dBFS) low, expected to be more than (-30.0 dBFS), loopback not working?
Rx calibration failed
Rx ch1 DC/IQ calibration failed: Loopback signal weak: not connected/insufficient gain?
Tx ch.B , BW: 20 MHz, RF output: BAND2, Gain: 63, loopb: internal
Rx DC auto   I:  -8, Q:  63, -28.9 dBFS
Rx DC manual I:  -6, Q:  63, -28.9 dBFS
RxTSP DC corrector enabled -78.3 dBFS
Receiver saturation search, target level: 20480 (-12.868 dBFS)
initial  PGA:  0, RXLOOPB:  7, -47.21 dbFS
adjusted PGA: 25, RXLOOPB: 15, -17.27 dBFS
Rx DC auto   I:  -6, Q:  63, -5.3 dBFS
Rx DC manual I: -10, Q:  63, -5.6 dBFS
RxTSP DC corrector enabled -52.0 dBFS
#0 Tx DC manual I:  -25, Q:   16, -65.5 dBFS
#1 Tx DC manual I:  -28, Q:   30, -67.3 dBFS
#2 Tx DC manual I:  -20, Q:   23, -63.7 dBFS
#0 Tx IQCORR: 128, -40.9 dBFS
#1 Tx GAIN_Q: 1693, -43.8 dBFS
#2 Tx IQCORR: 144, -45.3 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: |  -20 | 2047 | 144
Q: |   23 | 1693 |
Calibrate Tx duration: 467 ms
FPGA::SetInterfaceFreq tx:40.000 MHz rx:40.000 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
FPGA PLL[1] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:90 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:90 findPhase: 1
FPGA PLL[0] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
PLL Clock[1] PHCFG_START done
SDR configured in 1848ms
StopStreaming
/dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us

Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus
StopStreaming
ResetTimestamp
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
StartStreaming
Stream started ...
Total samples received: 19997696  signal amplitude: 0.03898  total samples sent: 19997696
/dev/LimeXTRX0_trx0 Tx: 160.763 MB/s | TS:20061952 pkt:78114 o:0 shw:26038/25964(+74) u:0(+0) l:0(+0) tsAdvance:+54016/+62865/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:19998720 pkt:78120 o:0(+0) l:0(+0) dma:26040/26044(4) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 161.252 MB/s | TS:40062208 pkt:156240 o:0 shw:52080/52006(+74) u:0(+0) l:0(+0) tsAdvance:+40960/+62878/+64768, f:0
Total samples received: 39998464  signal amplitude: 0.0380264  total samples sent: 39998464
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:40000512 pkt:156252 o:0(+0) l:0(+0) dma:52084/52088(4) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 161.252 MB/s | TS:60062464 pkt:234366 o:0 shw:12586/12512(+74) u:0(+0) l:0(+0) tsAdvance:+53248/+63064/+64768, f:0
Total samples received: 59999232  signal amplitude: 0.0410621  total samples sent: 59999232
/dev/LimeXTRX0_trx0 Rx: 161.240 MB/s | TS:60002304 pkt:234384 o:0(+0) l:0(+0) dma:12592/12592(0) swFIFO:2

Thank you very much for your help and time!

andrewback · 29 April 2024 18:56

Just to check, is this the same issue posted to the tracker:

github.com/myriadrf/LimeSuiteNG

Changing LOFrequency in dualRXTX and calibration

opened 12:45PM - 19 Apr 24 UTC

closed 08:46PM - 23 Apr 24 UTC

Jojeker

Hello, we are performing some tests with the new limesuiteNG development bran…ch on a LimeSDR XTRX. To this end, we execute the `dualRXTX` example which shows some output on our signal analyzer at 1.5GHz. However, if we change the `frequencyLO` variable to some other value in the allowed range (say 3.5GHz or 2.5GHz), then the output is not given. We also noticed, that enabling the calibration on RX and TX does fail, but we could not figure out why this is the case. The error code that we retrieve upon debugging is: `Rx ch%i DC/IQ calibration failed: %s` leading to a segmentation fault in the example. Is this an error in limesuiteNG or is additional configuration required to perform successful calibration? Thanks for your help! We attach the logs for 1.5GHz and 3.5GHz below: ### 1.5 GHz: ``` sens@nuc4:~/Downloads/LimeSuiteNG/vbuild ./bin/examples/dualRXTX Devices found : 0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000 Configuring device ... SetFrequencySXT, (1500.000 MHz)INT 111, FRAC 403298, DIV_LOCH 1, EN_DIV2_DIVPROG 1 Expected VCO 6000.00 MHz, RefClk 26.00 MHz Tuning VCOL : TuneVCO(SXT) ICT_VCO: 192 TuneVCO(SXT) - attempted VCO too low VCOL : failed to lock Tuning VCOM : TuneVCO(SXT) ICT_VCO: 192 TuneVCO(SXT) - searching interval [0:128] binary search: csw=64 cmphl=0 csw=96 cmphl=0 csw=112 cmphl=0 csw=120 cmphl=0 csw=124 cmphl=0 csw=126 cmphl=0 csw=127 cmphl=0 adjust with linear search: CSW interval failed to lock TuneVCO(SXT) - searching interval [128:256] binary search: csw=192 cmphl=3 csw=160 cmphl=0 csw=176 cmphl=3 csw=168 cmphl=2 csw=172 cmphl=2 csw=174 cmphl=2 csw=175 cmphl=2 adjust with linear search: csw=167 cmphl=0 CSW: lowest=168, highest=175, will use=171 choosing wider CSW locking range: low=168, high=175 TuneVCO(SXT) - confirmed lock with final csw=171, cmphl=2 VCOM : csw=171 tune ok Tuning VCOH : TuneVCO(SXT) ICT_VCO: 192 TuneVCO(SXT) - attempted VCO too high VCOH : failed to lock Selected: VCOM, CSW_VCO: 171 Sampling rate set(10.000 MHz): CGEN:80.000 MHz, Decim: 2^1, Interp: 2^1 INT 91, FRAC 322638, DIV_OUTCH_CGEN 14 VCO 2400.00 MHz, RefClk 26.00 MHz ICT_VCO_CGEN: 16 csw 172; interval [169, 175] FPGA::SetInterfaceFreq tx:20.000 MHz rx:20.000 MHz channel:0 FPGA SetPllFrequency: PLL[1] input:20.000 MHz clockCount:2 CLK[0] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 0 CLK[1] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 1 FPGA PLL[1] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz) FPGA PLL[1] PLLCFG_START FPGA PLL[1] PLLCFG_START done PLL Clock[0] PHCFG_START PLL Clock[0] PHCFG_START done PLL Clock[1] PHCFG_START PLL Clock[1] PHCFG_START done FPGA SetPllFrequency: PLL[0] input:20.000 MHz clockCount:2 CLK[0] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 0 CLK[1] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 1 FPGA PLL[0] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz) FPGA PLL[0] PLLCFG_START FPGA PLL[0] PLLCFG_START done PLL Clock[0] PHCFG_START PLL Clock[0] PHCFG_START done PLL Clock[1] PHCFG_START PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008 PLL Clock[1] PHCFG_START done SDR configured in 843ms StopStreaming /dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus StopStreaming ResetTimestamp SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99) SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99) StartStreaming Stream started ... /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:9996288 pkt:39048 o:0(+0) l:0(+0) dma:13016/13020(4) swFIFO:0 Total samples received: 9997312 signal amplitude: 0.325509 total samples sent: 9997312 /dev/LimeXTRX0_trx0 Tx: 77.679 MB/s | TS:10061824 pkt:37866 o:0 shw:12622/12548(+74) u:396(+396) l:18(+18) tsAdvance:-74240/+60247/+64768, f:0 /dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:19998720 pkt:78120 o:0(+0) l:0(+0) dma:26040/26044(4) swFIFO:0 Total samples received: 19999744 signal amplitude: 0.283218 total samples sent: 19999744 /dev/LimeXTRX0_trx0 Tx: 80.645 MB/s | TS:20064256 pkt:76938 o:0 shw:25646/25573(+73) u:396(+0) l:18(+0) tsAdvance:+54784/+62758/+64768, f:0 /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:29998080 pkt:117180 o:0(+0) l:0(+0) dma:39060/39064(4) swFIFO:1 Total samples received: 29997056 signal amplitude: 0.283389 total samples sent: 29997056 /dev/LimeXTRX0_trx0 Tx: 80.632 MB/s | TS:30061312 pkt:115989 o:0 shw:38663/38595(+68) u:396(+0) l:18(+0) tsAdvance:+52480/+62627/+64768, f:0 /dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:40000512 pkt:156252 o:0(+0) l:0(+0) dma:52084/52088(4) swFIFO:0 Total samples received: 40001536 signal amplitude: 0.28423 total samples sent: 40001536 /dev/LimeXTRX0_trx0 Tx: 80.645 MB/s | TS:40066816 pkt:155073 o:0 shw:51691/51616(+75) u:396(+0) l:18(+0) tsAdvance:+54784/+62693/+64768, f:0 /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:50002176 pkt:195321 o:0(+0) l:0(+0) dma:65107/65108(1) swFIFO:1 Total samples received: 50002944 signal amplitude: 0.28424 total samples sent: 50002944 /dev/LimeXTRX0_trx0 Tx: 80.632 MB/s | TS:50068480 pkt:194142 o:0 shw:64714/64639(+75) u:396(+0) l:18(+0) tsAdvance:+42496/+62567/+64768, f:0 /dev/LimeXTRX0_trx0 Rx: 80.669 MB/s | TS:60002304 pkt:234384 o:0(+0) l:0(+0) dma:12592/12600(8) swFIFO:0 /dev/LimeXTRX0_trx0 Tx: 80.620 MB/s | TS:60067072 pkt:233199 o:0 shw:12197/12126(+71) u:396(+0) l:18(+0) tsAdvance:+54784/+62698/+64768, f:0 Total samples received: 60003328 signal amplitude: 0.284678 total samples sent: 60003328 /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:70007808 pkt:273468 o:0(+0) l:0(+0) dma:25620/25620(0) swFIFO:5 /dev/LimeXTRX0_trx0 Tx: 80.657 MB/s | TS:70067968 pkt:272265 o:0 shw:25219/25147(+72) u:396(+0) l:18(+0) tsAdvance:+54016/+62719/+64768, f:0 Total samples received: 70007808 signal amplitude: 0.28273 total samples sent: 70007808 /dev/LimeXTRX0_trx0 Tx: 80.620 MB/s | TS:80070400 pkt:311337 o:0 shw:38243/38168(+75) u:396(+0) l:18(+0) tsAdvance:+54784/+62784/+64768, f:0 /dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:80007168 pkt:312528 o:0(+0) l:0(+0) dma:38640/38644(4) swFIFO:0 Total samples received: 80008192 signal amplitude: 0.28419 total samples sent: 80008192 /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:90008064 pkt:351594 o:0(+0) l:0(+0) dma:51662/51664(2) swFIFO:1 Total samples received: 90007552 signal amplitude: 0.28566 total samples sent: 90007552 /dev/LimeXTRX0_trx0 Tx: 80.632 MB/s | TS:90072064 pkt:350406 o:0 shw:51266/51192(+74) u:396(+0) l:18(+0) tsAdvance:+53248/+62713/+64768, f:0 Rx0: packetsIn: 390615 /dev/LimeXTRX0_trx0 Tx: 73.357 MB/s | TS:100061440 pkt:389427 o:0 shw:64273/64273(+0) u:396(+0) l:18(+0) tsAdvance:+51712/+62663/+64768, f:0 StopStreaming Tx Loop totals: packets sent: 389427 (0x0005F133) , FPGA packet counter: 389427 (0x0005F133), diff: 0, FPGA tx drops: 32 DeviceRegistry Removed: LitePCIe DeviceRegistry Removed: FTDI DeviceRegistry Removed: FX3 ``` (For this one we notice that there is a DC bias, which does not always occur (i.e., power cycling solves this issue until it reoccurs).) ### 3.5 GHz: ``` sens@nuc4:~/Downloads/LimeSuiteNG/vbuild$ ./bin/examples/dualRXTX Devices found : 0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000 Configuring device ... SetFrequencySXT, (3500.000 MHz)INT 130, FRAC 645277, DIV_LOCH 0, EN_DIV2_DIVPROG 1 Expected VCO 7000.00 MHz, RefClk 26.00 MHz Tuning VCOL : TuneVCO(SXT) ICT_VCO: 192 TuneVCO(SXT) - attempted VCO too low VCOL : failed to lock Tuning VCOM : TuneVCO(SXT) ICT_VCO: 192 TuneVCO(SXT) - attempted VCO too low VCOM : failed to lock Tuning VCOH : TuneVCO(SXT) ICT_VCO: 192 TuneVCO(SXT) - searching interval [0:128] binary search: csw=64 cmphl=0 csw=96 cmphl=0 csw=112 cmphl=0 csw=120 cmphl=2 csw=124 cmphl=2 csw=126 cmphl=2 csw=127 cmphl=2 adjust with linear search: csw=119 cmphl=2 csw=118 cmphl=0 CSW: lowest=119, highest=127, will use=123 TuneVCO(SXT) - searching interval [128:256] binary search: csw=192 cmphl=3 csw=160 cmphl=3 csw=144 cmphl=3 csw=136 cmphl=2 csw=140 cmphl=2 csw=142 cmphl=2 csw=143 cmphl=2 adjust with linear search: csw=135 cmphl=2 csw=134 cmphl=2 csw=133 cmphl=2 csw=132 cmphl=2 csw=131 cmphl=2 csw=130 cmphl=2 csw=129 cmphl=2 csw=128 cmphl=2 CSW: lowest=128, highest=143, will use=135 CSW is locking in one continous range: low=119, high=143 TuneVCO(SXT) - confirmed lock with final csw=131, cmphl=2 VCOH : csw=131 tune ok Selected: VCOH, CSW_VCO: 131 Sampling rate set(10.000 MHz): CGEN:80.000 MHz, Decim: 2^1, Interp: 2^1 INT 91, FRAC 322638, DIV_OUTCH_CGEN 14 VCO 2400.00 MHz, RefClk 26.00 MHz ICT_VCO_CGEN: 16 csw 172; interval [169, 175] FPGA::SetInterfaceFreq tx:20.000 MHz rx:20.000 MHz channel:0 FPGA SetPllFrequency: PLL[1] input:20.000 MHz clockCount:2 CLK[0] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 0 CLK[1] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 1 FPGA PLL[1] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz) FPGA PLL[1] PLLCFG_START FPGA PLL[1] PLLCFG_START done PLL Clock[0] PHCFG_START PLL Clock[0] PHCFG_START done PLL Clock[1] PHCFG_START PLL Clock[1] PHCFG_START done FPGA SetPllFrequency: PLL[0] input:20.000 MHz clockCount:2 CLK[0] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 0 CLK[1] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 1 FPGA PLL[0] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz) FPGA PLL[0] PLLCFG_START FPGA PLL[0] PLLCFG_START done PLL Clock[0] PHCFG_START PLL Clock[0] PHCFG_START done PLL Clock[1] PHCFG_START PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008 PLL Clock[1] PHCFG_START done SDR configured in 853ms StopStreaming /dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus StopStreaming ResetTimestamp SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99) SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99) StartStreaming Stream started ... /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:9998592 pkt:39057 o:0(+0) l:0(+0) dma:13019/13020(1) swFIFO:11/dev/LimeXTRX0_trx0 Tx: 80.124 MB/s | TS:10053376 pkt:39018 o:0 shw:13006/12941(+65) u:0(+0) l:0(+0) tsAdvance:+36352/+60618/+64768, f:0 Total samples received: 9990144 signal amplitude: 0.373463 total samples sent: 9990144 /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:19997952 pkt:78117 o:0(+0) l:0(+0) dma:26039/26040(1) swFIFO:3 /dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:20059648 pkt:78105 o:0 shw:26035/25962(+73) u:0(+0) l:0(+0) tsAdvance:+32512/+59868/+64768, f:1 Total samples received: 19996672 signal amplitude: 0.165747 total samples sent: 19996672 /dev/LimeXTRX0_trx0 Tx: 80.632 MB/s | TS:30059008 pkt:117165 o:0 shw:39055/38984(+71) u:0(+0) l:0(+0) tsAdvance:+48640/+60839/+64768, f:1 Total samples received: 29996032 signal amplitude: 0.165367 total samples sent: 29996032 /dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:29998080 pkt:117180 o:0(+0) l:0(+0) dma:39060/39064(4) swFIFO:2 /dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:40059904 pkt:156231 o:0 shw:52077/52005(+72) u:0(+0) l:0(+0) tsAdvance:+30208/+59809/+64768, f:0 Total samples received: 39996416 signal amplitude: 0.172751 total samples sent: 39996416 /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:39999744 pkt:156249 o:0(+0) l:0(+0) dma:52083/52084(1) swFIFO:3 /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:49997568 pkt:195303 o:0(+0) l:0(+0) dma:65101/65104(3) swFIFO:0 Total samples received: 49997824 signal amplitude: 0.163238 total samples sent: 49997824 /dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:50062336 pkt:195303 o:0 shw:65101/65029(+72) u:0(+0) l:0(+0) tsAdvance:+39424/+60189/+64768, f:0 /dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:59999232 pkt:234372 o:0(+0) l:0(+0) dma:12588/12592(4) swFIFO:0 /dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:60062464 pkt:234366 o:0 shw:12586/12517(+69) u:0(+0) l:0(+0) tsAdvance:+47104/+61063/+64768, f:2 Total samples received: 60000256 signal amplitude: 0.164881 total samples sent: 60000256 /dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:69998592 pkt:273432 o:0(+0) l:0(+0) dma:25608/25616(8) swFIFO:9 Total samples received: /dev/LimeXTRX0_trx0 Tx: 80.663 MB/s | TS:70055680 pkt:273402 o:0 shw:25598/25540(+58) u:0(+0) l:0(+0) tsAdvance:+39424/+59810/+64768, f:0 69992448 signal amplitude: 0.156581 total samples sent: 69992448 /dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:80000256 pkt:312501 o:0(+0) l:0(+0) dma:38631/38636(5) swFIFO:1 Total samples received: 80000000 signal amplitude: /dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:80063488 pkt:312495 o:0 shw:38629/38563(+66) u:0(+0) l:0(+0) tsAdvance:+47872/+60980/+64768, f:1 0.173769 total samples sent: 80000000 /dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:90003456 pkt:351576 o:0(+0) l:0(+0) dma:51656/51660(4) swFIFO:1 Total samples received: /dev/LimeXTRX0_trx0 Tx: 80.651 MB/s | TS:90068992 pkt:351579 o:0 shw:51657/51584(+73) u:0(+0) l:0(+0) tsAdvance:+40192/+61090/+64768, f:0 90005504 signal amplitude: 0.162127 total samples sent: 90005504 Rx0: packetsIn: 390624 /dev/LimeXTRX0_trx0 Tx: 73.301 MB/s | TS:100056064 pkt:390591 o:0 shw:64661/64661(+0) u:0(+0) l:0(+0) tsAdvance:+32512/+59499/+64768, f:0 StopStreaming Tx Loop totals: packets sent: 390591 (0x0005F5BF) , FPGA packet counter: 390591 (0x0005F5BF), diff: 0, FPGA tx drops: 0 DeviceRegistry Removed: LitePCIe DeviceRegistry Removed: FTDI DeviceRegistry Removed: FX3 ```

?

sens118 · 30 April 2024 10:29

Correct, we figured that the issue might be related and thus asked for reference. At least it came up in subsequent tests.

andrewback · 30 April 2024 10:32

Thanks, just so we know this is not a separate issue.

sens118 · 1 May 2024 17:41

Hello again,

we were asking in the Github issue about flashing the LimeSDR XTRX with Vivado 2022 via JTAG and were advised to ask here. Specifcally, we are unsure about the steps presented in GitHub - myriadrf/LimeSDR-XTRX_GW: LimeSDR XTRX gateware project. to program the FPGA of the LimeSDR if it cannot be programmed via limeFLASH.

We followed specifically these steps:

Connect USB-C for power
Use Vivado 2022 standard with Atrix 7 included
Connect the 6 pins of JTAG to our programmer
Open Hardware Manager → Auto connect

Any insights on what might be going wrong would be immensely helpful. Thanks for your efforts!

andrewback · 2 May 2024 08:31

The forums are used for support and should be the first port of call, only logging issues on the tracker when a bug has been identified.

Tagging @VytautasB, who should be able to help.

VytautasB · 2 May 2024 10:02

Hello @sens118,

not sure if I understand what issue are you facing when programming FPGA via JTAG?

As described in GitHub repo you will need PCIe Adapter to access JTAG chain, because LimeSDR-XTRX itself does not have JTAG header, only exposed pads.

When you have JTAG cable connected - it is standard programming procedure in Vivado software as for any other Xilinx device.

sens118 · 2 May 2024 18:07

Thanks for the reply! We managed to flash the gateware via JTAG with openFPGAloader at GitHub - trabucayre/openFPGALoader: Universal utility for programming FPGA.

Our procedure is as follows:

We use a CH347 programmer to perform JTAG programming https://akizukidenshi.com/goodsaffix/ch347.pdf.2
We install openFPGAloader:
We connect the correct pins to the CH347
We run the following command:

openFPGALoader -c ch347_jtag -b xtrx -f ../flash_programming_file.bin

This way we flashed the gateware with a given bitstream. We were able to flash the latest bitstream without any problems.

Thanks again for the help!