Phase Locking Problem

I am trying to demodulate a simple standart AM signal that is in the form (1+sin(2π1000t))sin(2π30e6t+Φ) using LimeSuite API. This means 30MHz sine wave carrier and 1kHz sine wave message. I am using two synchronized signal generators, one being a reference clock input and the other one generating the AM signal. Since AM modulation is essentially the same as IQ modulation but the Q part is equal to zero, I should only see the noise as the Q part. The problem is neither I nor Q is zero but they are sine waves with random amplitude on every run. This means that the the carrier wave and LO signal is not in phase even though I use a reference clock. How can I make them in phase? Doesn’t limeSDR supposed have phase detectors and correctors?

By the way, without the reference clock, the output is a total meaningless mess, I would expect a better result this way also.

Thanks in advance for your replies.

Really, can anybody on this forum help me on this issue? I’ve read the datasheet thoroughly and could not find a solution anywhere else.

To generate a pure “I” signal you need input two signals exactly in phase at fc + w and fc - w or perhaps you can jumper it in at some point on the board.

I have a similar problem with an IQ modulated signal. How do we control phase locking?