PC to FPGA USB interface endpoint query

#1

Hello,
This with reference to the LimeMini SDR board which uses a FT601 to bridge the PC to the FPGA.
As per the FT601 configuration endpoint 0x02 is configured as a BLOCK endpoint with a packet size of 0x0200 (512) Bytes.
However the Nios code indicates that the commands are being received as packets of 64 Bytes.
In short, the URB is set to 512 as per the endpoint descriptor but the Nios code indicates otherwise. Please guide.

I guess this is a question not relevant to the operation of the LMS7002M but since the developers of the system are here I hope to get some help.
Thanks again for sharing your expertise.

#2

Hi @EnthuMan,

Yes, NIOS sends 64 bytes packet. We use short packet option to achieve this.

#3

Hello @Zack,
EP83 in the FPGA (meant for transferring Rx data from FPGA to PC) is configured for a packet size of 2048 Bytes but the endpoint descriptor is set to 1024 Bytes (when connected to USB3.0) and 512 Bytes (when connected to USB2.0).
May I ask you to please guide on how it works (the mis-match)
Regards,

#4

Hi @EnthuMan,

There are a lot of “packets”, hence confusion. Will try to my best to explain:

  1. IQ data are packed to packets of 4096 bytes in FPGA/software;
  2. FTDI USB MCU features 2048 byte internal DMA buffer hence FPGA divides our 4096 byte packet to 2x 2048 chunks and sends to FTDI;
  3. Then USB specification comes into the game. USB3 sends data packets which are 1024 bytes long; USB2 - 512.

Hope this explains.

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