I am trying to understand the interface between the i.mx6 and FPGA that is used here, so I will be able to tweak it a little bit for my needs. I can see that the design assumes that BCLK is continuous as BCM bit is set in the novena_rf_eim driver. The SRD and SWR bits are also set so the EIM interface is synchronous, but according to the IMX6 datasheet, BCM =1 is only possible in async mode and SRD and SWR are discarded. So, the question is - are you using async mode for the communication?
I did the FPGA design for the novena RF. I largely inherited the EIM bus configuration, although a few tweaks were needed for timing adjustment. Its possible that some of the configuration bits were set for testing and may not make sense any more, but the code setting them remained. Sorry for the non-specific answer, its been a while since I looked at the bus config.
In any case, the intention was that the reads and the writes should be setup for synchronous mode and the BCLK should be continuous. In the FPGA, the EIM bus is muxed into one of several block rams and a register interface – which can be accessed through memory mapped reads and writes on the arm.
