I am looking at trying to lock multiple boards together using a common oscillator.
From looking at the circuit diagram it seems I need to add resistor R151 to output the 30.72 MHz clock
and to remove resistor R158 and add resistor R155 to allow the 30.72 MHz clock to be fed
to IC24 Si5351 then of course I need to reprogram it to use the different input clock frequency.
Unfortunately these resistors are not marked on the silk screen (or I can’t see them).
I am working from a revision 1.4 schematic but have revision 1.4s PCBs.
Any help / comments from the Lime design team would be appreciated
I found where the resistors are (next to DDR #1) they are shown on the silkscreen but opposite where they
are on a bit of blank board with a big 1 next to it.
Next I need to figure out what the ramifications will be changing the clock from 25 MHz to 30.72 (other than
program change to the clock generator). There must be some ramification otherwise Lime could have saved
themselves the cost of the extra 25 MHz clock chip by using the 30.72 MHz instead.
Maybe not as the Si5351C requires the 25/27 MHz crystal for it’s internal logic
if I have read the data sheet correctly.
I have modified one of my boards to connect the 30.72 to the clkin pin of the
Si5351C. Next I will see what needs to be done to change the reference in
software.
Another hurdle will be aligning the sample blocks from the 4 boards.
I have not thought about that too much yet.
Well I think I am wasting my time on this as I have looked at the VHDL code and as far
as I can make out CLK0 from the Si5351C is used to do 2 things
indicate the FPGA is alive and provide a 27 MHz reference to the ddr_ref_clk.
The other clocks (except CLK4 which is unused) drive counters which appear only to be used for testing.
The comments in the code are very sparse and I am more familiar with Verilog than VHDL.
I am beginning to think that the sampling is derived from the 30.72 MHz LTE clock.
