I have been studying a bit.
You told " but could not find where the I&Q and CLK are generated".
It’s not easy to understand, but maybe @Zack can help us.
In the FPGA design, there is a pair of signal and bus, that I suppose come from the LMS chip
LMS_DIQ2_D and LMS_DIQ2_IQSEL2
In the entity rx_path, this signal is packed into a 64 bits data packet (in the rx_pct_data_v2 component), and sent by the rx_pct_data bus to the FX3_slaveFIFO component.
From there, it’s sent to the PC by the USB3.
So, I suppose, we should take the LMS_DIQ2_D data , or the rx_pct_data and do the FFT over that.
My questions for the experts are:
- is my understanding correct?
- what happens exactly in the rx_pct_data? why the output is of 64 bits?
Can anyone explain to us how it works? is there a technical note or something similar to study from?