Minor Modifications to the fpga gateware

Hi All,
I want to do some minor modifications to the FPGA Gateware:

  1. Serializing the I&Q data and sending them along with the Clock to the GPIO. (For demodulation in another FPGA board).

  2. I want reduce the I&Q rate send to the PC. I am only using I&Q for spectrum monitoring and I don’t need realtime sampling.

My question is: I skimmed through the code but could not find where the I&Q and CLK are generated. For step 2 is decimation appropriate or do I need averaging?

Thank you in advance.

Hi booth!

  1. If the purpose is demodulation, I suppose you’re going to decimate first, then serialize and finally send the signal to the GPIO. Is it correct?

  2. I would like to do the same, and put a FFT core inside the FPGA.
    According to the forum, it seems there not enough space in the FPGA to do it, but I didn’t try untill now.
    If you do it, please tell me!

About your questions:

  • “is decimation appropriate?” It depends. Which is the maximum frequency you want to monitor?
  • “do I need averaging?” It depends. Do you mean averaging of FFT results?


Hi nemo,

  1. If I sample at 2 MSPS I would like to decimate it by 2 getting 1 MSPS,
    using 2 GPIO as data output, I will need 1MSPS*24/2 = 12 MHz clock signal.
    Then I will try to deserialize/ demodulate the 1MSPS signal in another FPGA.

  2. For spectrum monitoring I don’t need the display to be fast. Something like 5 FPS would be more than enough. Is there something that I can do to reduce the full rate so that the USB traffic and FFT CPU usage.

Hi booth,

  1. OK, I understand what you want to do, and I imagine you can use the GPIOs do it.

What I really don’t know is how you can generate a 12MHz clock, from a 1MHz clock.
A trick could be to sample at 12 MHz (with associated clock at 12MHz), and then decimate with a factor of 12. After that serialize and redirect to GPIOs.

  1. Do you want to do the FFT in the FPGA?
    If the answer is YES:
    you could do continuosly FFTs, then use an algorithm to process the different results, and send by USB only the final result.

For example, you can do FFTs of 1024 point. Each FFT will give you 1024 complex numbers as result, one for each frequency bin.
You could create a “total FFT result” composed by 1024 values, one per frequency bin, corresponding to the maximum of X FFT results.
Sending only the total FFT result, you’ll reduce the USB traffic of a X factor, without loosing information.

If the answer is NO: just reduce the sampling frequency.

Did you find in which point of the FPGA the received data are prepared to be sent?
I’m looking for it.

Hi booth!

I have been studying a bit.
You told " but could not find where the I&Q and CLK are generated".
It’s not easy to understand, but maybe @Zack can help us.

In the FPGA design, there is a pair of signal and bus, that I suppose come from the LMS chip

In the entity rx_path, this signal is packed into a 64 bits data packet (in the rx_pct_data_v2 component), and sent by the rx_pct_data bus to the FX3_slaveFIFO component.
From there, it’s sent to the PC by the USB3.

So, I suppose, we should take the LMS_DIQ2_D data , or the rx_pct_data and do the FFT over that.

My questions for the experts are:

  • is my understanding correct?
  • what happens exactly in the rx_pct_data? why the output is of 64 bits?
    Can anyone explain to us how it works? is there a technical note or something similar to study from?

thank you