MIMO DDR mode LML interface

I am looking for the following for the interface between my FPGA and LMS chip.

  1. BB2RF DDR mode where only FCLK1 is used (Port 1 is used for BB2RF) like in Fig 38 of the datasheet.
  2. RF2BB DDR mode where only MCLK2 is used (Port 2 is used for RF2BB) like in Fig 37 of the datasheet.

Referring to the LimeLight modes description document, I found the following:
3.1 TRXIQ MIMO DDR Mode (RF2BB) without FCLK (looks like this meets my requirement of RF2BB).

We are feeding the FPGA a clock from the same clock distribution chip that feeds xclk_tx, xclk_rx in the LMS.

However I couldn’t find anything for BB2RF without MCLK. 3.4 speaks about BB2RF but requires using MCLK to generate FCLK inside the BB/FPGA. I am unable to understand this requirement. Fig 37 of the datasheet seems logical (and does not have a requirement of MCLK). Fig 54 of the datasheet also shows the same interface (MCLK1 is unused).

We looked at the FPGA code for the LimeMini and MCLK1 is not used in the design. FCLK1 is derived from MCLK2. Please confirm.

Please advise.

Requirement to derive FCLK from MCLK is for frequency synchronization just to avoid small LML FIFO overflow if FCLK and MCLK frequencies are slightly different.

Is it possible to find out if there is a FIFO overflow occurring for our configuration?
Our FPGA is using a clock from a clock distribution chip that is also feeding the LMS.
We could use the MCLK2 to feed the PLL inside the FPGA to generate the FCLK1. Will that be ok?

There is no such possibility.

Yes, that should work.