I am trying to determine what the minimum rx/tx path latency for the LMS7002 could be.
In other words, If I ignore any latency introduced by our baseband processor, what would be the latency from tx digital baseband data going to the LMS7002 to rx digital baseband data being received from the LMS7002 interface assuming a short loopback of RF output to input.
I understand that the filter configurations, sample rate, etc will change this, but am trying to determine what the minimum could be assuming all parameters are configured to give minimum delay.
To give some background, we have an application that is very sensitive to latency in the rx/tx paths and are currently looking for an alternative to the AD9364 since we are running into some unspecified latencies with this part.
Setting aside other latency in our baseband processor, we are trying to achieve <300ns from tx baseband data out to rx basband data in at ~60M Sample/s data rate.
As you correctly mentioned, the latency of digital part will be dependent on what digital modules are engaged or bypassed. As a starting point I can say that it is 10 clock cycles for each Tx and 10 clock cycles Rx if all the digital modules are bypassed. Convert it to time, while I do not know what frequency you are going to run.
Let me know if you are going to use any of digital modules. Will update on latency change.
As mentioned, our rx/tx data rate to the baseband processor would target 60MS/s.
We would not be using the programmable G.P. FIR1-3 on the TX or RX path and would only be using the HBx decimation filters as needed to arrive at the 60MHz rate with a minimum latency.
So If I understand correctly, since the maximum ADC rate is 160MHz, we would either use an ADC rate of 60MS/s and bypass all HBF decimation or use an ADC rate of 120MS/s with HB1 decimation of 2. Likewise for the tx path except the DAC rate can go up to 640MS/s.
Is the 10 clock cycles you mention at the actual ADC/DAC data rate or the clock rate? For example, I understand the ADC has a fixed div. by 4 on its clock so do you mean the latency is 10 cycles at 120MHz or 640MHz?
Or is the clock cycles you mention at the baseband data rate (after any decimation for RX path and before any interpolation for tx path).
Correct, missed it somehow…[quote=“abadobid, post:7, topic:1289”]
So If I understand correctly, since the maximum ADC rate is 160MHz, we would either use an ADC rate of 60MS/s and bypass all HBF decimation or use an ADC rate of 120MS/s with HB1 decimation of 2. Likewise for the tx path except the DAC rate can go up to 640MS/s.
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Before answering it It would be nice to know RF BW.[quote=“abadobid, post:7, topic:1289”]
Is the 10 clock cycles you mention at the actual ADC/DAC data rate or the clock rate? For example, I understand the ADC has a fixed div. by 4 on its clock so do you mean the latency is 10 cycles at 120MHz or 640MHz?
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Ten clock cycles of TSP frequency when interpolation/decimation bypassed (in this case TSP frequency is the same as ADC/DAC sample rate).
