LMS7002 Configuration via FPGA/SPI and example.ini

Dear Lime Team (@andrewback, @zack) ,

we have some trouble configuring the LMS7002M chip via the FPGA in order to receive I/Q data (at any frequency). We can not use the FX3 (SPI interface only) and want to command as well as read the LMS7002M through an external ARM based uC. The uC is connected through the FPGA GPIO Pins and the FPGA Gateware is adpated as explained 2 sections below.

However, we have some trouble with the configuration of the LMS7002M transceiver chip. The short story is that we are trying to configure the LMS with an external micro controller via the FPGA in order to send I/Q data of Port 1 (receive only at any frequency) via SPI to the FPGA’s GPIO Pins. However, although the LMS can be configured it does not send any data. So we are wondering if any other steps are needed to configure the LMS to send RX data to the FPGA? We are guessing that the clock frequency may need to be written into one of the registers, too?

The setup to configure the transceiver is the following:
PC (example.ini) --> FTDI chip / Uart --> external uC --> SPI (via GPIO Pins) --> FPGA --> SPI —> LMS7002M.

The test .ini file from the Forum (example.ini) is utilized: https://wiki.myriadrf.org/LimeSDR-USB_Quick_Test

The PC sends the example.ini via FTDI to the uC, which converts it into the correct data format and then sends it to the FPGA (via LimeSDR GPIOs). The FPGA Gateware has been adopted to forward the data to the LMS transceiver. The registers in the transceiver are than read in order to verify the correct setup. Sometimes there are wrong numbers in the LMS registers… However, the FPGA than reads the DIQ interface and passes this data on to another external SPI interface (utilizing the GPIOs) --> see flow depicted below.

The setup to receive the I/Q data is:
LMS7002M --> DIQ --> FPGA --> SPI (via GPIO Pins)

Is there theoretically anything else needed than just the “example.ini” file in order to make the LMS talk with the FPGA and transmit the I/Q data? (Btw. the Clock generator is working, I programmed it via I2C every time the board powers up and implemented a control LED which indicates that the FPGA works.)

Also the “example.ini” mentions the clock frequency at the very bottom of the file. Unfortunately it does not tell me the register and value for the LMS. I deleted this out of the file, could this be the reason? Is there any register which needs to be filled in order to tell the LMS that the clock frequency is 30.72 MHz?

Thank you very, very much for your help!
Best regards,

1 Like

Hello @Sombrero,

As far as I understand you are using custom FPGA gateware for this purpose, right? If yes:

  1. How is your interface between FPGA and LMS7002M implemented? Do you supply FCLK clock to LMS7002M?
  2. Do you configure CGEN to the required frequency?

You need to know the reference frequency to calculate control words for LMS7002M PLL’s (RxPLL, TxPLL and CGEN).

Actually, I would suggest to study these examples to understand what bare minimum do you need to get the samples from LMS7002M.

Hello Zack,

thank you very much. Yes we looked at the example. Just to clarify: We are not using any C interface, we are just passing data from the uC to through the FPGA onto the LMS SPI bus and registers. The way I see this we should be able to fully configure the LMS that way, correct?

For the FPGA to LMS interface: We are using nearly the same interface as for the LimeSDR GW, just that we extract the I/Q data from the DIQ input, and send the I and correlating Q portion after each other via SPI. Ofcourse we are slower than with the FIFO and FX3 that way, but the data rate should be sufficient for our application though.

We do supply the FCLK to the LMS. And the reference frequency is also 30.71 MHz from the identical Rakon oscillator.

However, we did not looked into CGEN and will do that. :slight_smile: Thank you for the hint.
Do you have any other suggestions and is it possible to fully configure the LMS via the SPI interface just by writing in its registers? (as mentioned at the beginning)

Thank you for your helpful and very quick reply! :wink:

@Zack @andrewback

could it be that there are frequency dependent registers for the internal clock generator of the LMS7002M? Unfortunately we got confused while studying the data sheet. In our case the REFCLK is 30.72 MHz, supplied by the Rakon oscillator. Is the MCLK active as soon as the CGEN is supplied with a reference clock? (see block diagram below, source: LMS7002M datasheet)


Zack, I couldn’t figure out what the frequency dependent registers are out of the sample code. Could you or anyone else give a hint where the frequency dependent register values are stored and how they can be changed?

Basically we are just trying to get our LMS7002 to speak with us and send us some RX data. However, we must have missed something since the MCLK is not working.