LMS6002 - big problem with PLL lock time for FDD and TDD modes

System Development
1

Hello, friends.
I have a problem with PLL lock time in LMS6002 chip.

In FDD mode PLL locks fast (or just not out from locking) and i can work perfect.

But in TDD mode i see that PLL lock time is extremelly greater then declarated ~8us (loop filter soldered for this parameters: charge pump current 2400mA, 100kHz bandwidth, VCO2 used). In fact it around 500us! So, as result my TDD system have failures…

I found Google group with similar topic (https://groups.google.com/forum/#!topic/limemicro-opensource/lWYvjcbRlCQ), but it have no answers to this question, the topic just died.
Due to fantastic problems with this chip i request community help. Hope you can help me )

Thanks a lot.

2

Hi @zlo,

Are you using some custom designed board? Can you share schematic if yes?

3

Yes, i use my custom board. I know about FAQ recommendations and we made all recommended changes.
But still have big lock time.

0
0.jpg5256×3718 742 KB