Hi,
I have maybe a little strange question, but I’d like to understand this. Some time ago (month or two) I had a problem with LMS_SendStream call. When I was calling it too quickly without meta (or with waitForTimestamp set to false) the samples seemed to be overwritten without being actually transmitted - e.g. following loop:
while(…){
n = read_from_file_to_buffer(buf);
LMS_SendStream(&tx_stream, buf, n, NULL, 1000 );
}
The speed of sending samples to LimeSDR-mini was limited only by the hw (cpu, usb, file i/o, etc.). LMS_GetStreamStatus reported linkRate multiple times bigger than what was appropriate to the used sample rate.
I solved it by using waitForTimestamp and increasing the timestamp by what was returned by LMS_SendStream.
But now I cannot replicate this behavior and the loop described above is working as I originally expected - the samples are transmitted correctly.
Was there a bug like this fixed? I cannot find any reference to anything like this. Or am I missing something else? I don`t have the original code any more, but I believe that the one I have is similar enough.
What is the correct behavior? I`d like to know how LMS_SendStream is supposed to be used. Is it OK to call it without meta (or with waitForTimestamp set to false) without risk that samples will be lost (assuming other conditions, like e.g. USB speed, are good enough)?
We were not aware of such bug. What board do you have (LimeSDR-USB or -Mini)? Recently, there has been some fixes in FPGA that dealt with issues when packet synchronization is disabled but none of the issues were similar to what you describe.
NULL can be passed as metadata (it defaults to waitForTimestamp=false, flushPartialPacket=false, timestamp=0).
When synchronization to timestamp is disabled (waitForTimestamp=false) Tx data rate should be limited by hardware sample rate.
So if I understand it correctly, if I don`t want synchronization between RX and TX, I can pass NULL as metadata to LMS_SendStream and it should work correctly. Right now it does, to there is actually now problem, I just wanted to understand. Maybe the fixes in FPGA solved this problem. Is there some simple way how test it?
