I downloaded and installed Quartus Prime Lite Edition Version 15.1.0 Build 185, with Cyclone IV device support and then installed the update to patch it to 15.1.2 Build 193. I then downloaded and extracted the zip file for the “LimeSDR-USB_GW” master branch from github. Double clicked on “lms7_trx.qpf” and ran a compile and got the same timing messages as you showed in the image in your original post highlighted in red.
I just assumed that it was because there are three fundamental clock sources on the LimeSDR-USB board: XO2 (VCTCXO 30.72MHz ±1 ppm initial; ±4 ppm stable - mostly used by LMS7002M ), XT1 (19.2MHz ±30ppm - FX3 probably needed for DFU mode, I’m not sure I’ve not looked into it at all) and XT2 (25MHz ±20ppm which is fed into a clock generator, Si5351C, to provide timing almost everywhere else that is digital) and that the human designers knew more than the Quartus Prime software at least when it came to timing in their design. (ref: https://wiki.myriadrf.org/LimeSDR-USB_hardware_description#Clock_distribution ; the schematic and Bill Of Materials). I did not bother to look into it at all, because I felt that I would need to fully understand the datasheet for the EZ-USB FX3, the EP4CE40F23C8N FPGA, the public document of the registers in the LMS7002M chip and I’d also need to read and fully understand all the gateware code. And learn my way around Quartus Prime a bit better than I currently do. At least one of the signals, to me anyhow, looks like it may be unused outside the FPGA FX3_PCLK_VIRT_OUT, but like I’ve said I’ve not looked into it at all.